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公开(公告)号：US20210279010A1
公开(公告)日：2021-09-09
申请号：US17331357
申请日：2021-05-26
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Eric Kwok Fung Yuen , Zhi Ping Yu , Guanzhong Wang
Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.
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公开(公告)号：US11029883B2
公开(公告)日：2021-06-08
申请号：US16484066
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Eric Kwok Fung Yuen , Zhi Ping Yu , Guanzhong Wang
Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.
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公开(公告)号：US11604607B2
公开(公告)日：2023-03-14
申请号：US17331357
申请日：2021-05-26
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Eric Kwok Fung Yuen , Zhi Ping Yu , Guanzhong Wang
Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.
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公开(公告)号：US20200233606A1
公开(公告)日：2020-07-23
申请号：US16484066
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Eric Kwok Fung Yuen , Zhi Ping Yu , Guanzhong Wang
Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.
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