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公开(公告)号：US11868245B2
公开(公告)日：2024-01-09
申请号：US17272113
申请日：2020-09-21
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Bin Zhao , Jianxiong Huang
CPC classification number: G06F12/0246 , G06F12/0623 , G06F13/1668 , G06F2212/7201 , G06F2212/7203
Abstract: Devices and techniques for improving memory access operations of a memory device are provided. In an example, a method can include loading multiple LBA-to-physical address (L2P) regions of an L2P table from memory arrays of the memory device to a mapping cache in response to determining the LBA of the memory access command is not within the L2P region including of a mapping cache. When the memory access command is a sequential command, the multiple L2P regions loaded to the mapping cache can provide improved memory access performance.
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公开(公告)号：US11455245B2
公开(公告)日：2022-09-27
申请号：US16076288
申请日：2017-12-11
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Giuseppe D'Eliseo , Lalla Fatima Drissi , Giuseppe Ferrari , Eric Kwok Fung Yuen , Massimo Iaculo
IPC: G06F12/02 , G06F12/1009
Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US11169917B2
公开(公告)日：2021-11-09
申请号：US16742215
申请日：2020-01-14
Applicant: Micron Technology, Inc.
Inventor： Giuseppe D'Eliseo , Luigi Esposito , Xinghui Duan , Lucia Santojanni , Massimo Iaculo
Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.
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公开(公告)号：US20210182189A1
公开(公告)日：2021-06-17
申请号：US16076288
申请日：2017-12-11
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Giuseppe D'Eliseo , Lalla Fatima Drissi , Giuseppe Ferrari , Eric Kwok Fung Yuen , Massimo laculo
IPC: G06F12/02 , G06F12/1009
Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US20210181940A1
公开(公告)日：2021-06-17
申请号：US16077175
申请日：2017-12-13
Applicant: Micron Technology, Inc.
Inventor： Zhao Cui , Eric Yuen , Guan Zhong Wang , Xinghui Duan , Hua Chen Li
Abstract: Devices and techniques for variable width superblock addressing are described herein. A superblock width, specified in number of planes, is obtained. A superblock entry is created in a translation table of a NAND device. Here, the superblock entry may include a set of blocks, from the NAND device, that have the same block indexes across multiple die of the NAND device. The number of unique block indexes are equal to the number of planes and in different planes. A request, received from a requesting entity, is performed using the superblock entry. Performing the request includes providing a single instruction to multiple die of the NAND device and multiple data segments. Here, a data segment corresponds to a block in the set of blocks specified by a tuple of block index and die. A result of the request is then returned to the requesting entity.
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Patent Agency Ranking
公开(公告)号：US11029883B2
公开(公告)日：2021-06-08
申请号：US16484066
申请日：2018-12-28
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Eric Kwok Fung Yuen , Zhi Ping Yu , Guanzhong Wang
Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.
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公开(公告)号：US11989456B2
公开(公告)日：2024-05-21
申请号：US17771668
申请日：2019-12-31
Applicant: Micron Technology, Inc.
Inventor： David Aaron Palmer , Xinghui Duan , Massimo Zucchinali
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F12/0246 , G06F2212/7202
Abstract: A computing system (100) having a storage system that includes a storage device (130) and a host device (105), where the host device (105) is configured to issue memory access commands to the storage device (130). The computing system (100) further includes a prediction system (190) comprising processing circuitry that is configured to perform operations that cause the prediction system (190) to identify one or more components of the storage system (918) that limit random rad performance of the storage system (918). The operations further cause the prediction system (190) to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system (918). The operations additionally cause the prediction system (190) to execute the model in a simulation of the storage system (918) to generate a random read performance parameter for the storage system (918).
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公开(公告)号：US11663120B2
公开(公告)日：2023-05-30
申请号：US17521340
申请日：2021-11-08
Applicant: Micron Technology, Inc.
Inventor： Giuseppe D'Eliseo , Luigi Esposito , Xinghui Duan , Lucia Santojanni , Massimo Iaculo
CPC classification number: G06F12/0246 , G06F12/0253 , G06F12/0292 , G11C16/10 , G06F2212/7201 , G06F2212/7205
Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.
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公开(公告)号：US11604607B2
公开(公告)日：2023-03-14
申请号：US17331357
申请日：2021-05-26
Applicant: Micron Technology, Inc.
Inventor： Xinghui Duan , Eric Kwok Fung Yuen , Zhi Ping Yu , Guanzhong Wang
Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.
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公开(公告)号：US20220357877A1
公开(公告)日：2022-11-10
申请号：US17869262
申请日：2022-07-20
Applicant: Micron Technology, Inc.
Inventor： Huachen Li , Xu Zhang , Zhong Xian Li , Xinghui Duan , Xing Wang , Tian Liang
IPC: G06F3/06 , G06F12/02 , G06F12/0882
Abstract: Devices and techniques for data removal marking in a memory device are described herein. A delete command can be received at the memory device. A count of data portions in the delete command can be compared to determine whether the count is below a threshold. In response to determining that the count of data portions is below the threshold, the data portions can be written to a buffer. When a buffer full event is detected, a segment of an L2P data structure can be loaded into working memory of the memory device. Then, each record in the segment of the L2P data structure that has a corresponding entry in the buffer can be updated to mark the data as removable (e.g., invalid).
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