公开(公告)号：US11327763B2

公开(公告)日：2022-05-10

申请号：US16898938

申请日：2020-06-11

Applicant: Microsoft Technology Licensing, LLC

Inventor： Arthur Perais ,  Shivam Priyadarshi ,  Yusuf Cagatay Tekmen ,  Rami Mohammad Al Sheikh ,  Vignyan Reddy Kothinti Naresh

IPC: G06F9/38 ,  G06F9/30

Abstract: Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor is disclosed. A processor provides producer instructions and consumer instructions to a steering circuit that steers the program instructions to clusters of instruction execution circuits. An input value provided to a consumer instruction may be a produced value of a producer instruction, creating a dependency. The steering circuit steers a producer instruction to a first cluster and, in response to receiving the consumer instruction and the predicted value of the producer instruction, provides the predicted value to at least a second cluster and steers the consumer instruction to the second cluster for execution with the predicted value as the input value. A consumer instruction can be executed in a different cluster than a producer instruction without a cluster-to-cluster latency penalty, which allows the instruction loads to be better balanced among the clusters for higher processor throughput.

公开(公告)号：US11061824B2

公开(公告)日：2021-07-13

申请号：US16558843

申请日：2019-09-03

Applicant: Microsoft Technology Licensing, LLC

Inventor： Vignyan Reddy Kothinti Naresh ,  Arthur Perais ,  Rami Mohammad Al Sheikh ,  Shivam Priyadarshi

IPC: G06F12/12 ,  G06F12/084 ,  G06F9/30 ,  G06F9/54 ,  G06F12/0837

Abstract: Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative is disclosed. The updating of at least one cache state in the cache memory resulting from a data request is deferred until the data request becomes non-speculative. Thus, a cache state in the cache memory is not updated for requests resulting from mispredictions. Deferring the updating of a cache state in the cache memory can include deferring the storing of received speculative requested data in the main data array of the cache memory as a result of a cache miss until the data request becomes non-speculative. The received speculative requested data can first be stored in a speculative buffer memory associated with a cache memory, and then stored in the main data array if the data request becomes non-speculative.

公开(公告)号：US10896041B1

公开(公告)日：2021-01-19

申请号：US16582008

申请日：2019-09-25

Applicant: Microsoft Technology Licensing, LLC

Inventor： Shivam Priyadarshi ,  Arthur Perais ,  Vignyan Reddy Kothinti Naresh ,  Yusuf Cagatay Tekmen ,  Rami Mohammad Al Sheikh ,  Rodney Wayne Smith

IPC: G06F9/30 ,  G06F9/38

Abstract: Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices is disclosed. In one exemplary embodiment, a processor-based device provides a move-immediate logic circuit that detects a move-immediate instruction comprising an immediate value and a destination register. For frequently encountered immediate values, the move-immediate logic circuit allocates a physical register from an immediate physical register file (IPRF), and writes an IPRF tag corresponding to the allocated IPRF register into a most-recent mapping table (MRT) entry for the destination register. Subsequent move-immediate instructions embedding the same immediate value, as well as other dependent instructions, may then obtain the immediate value from the IPRF register by accessing the MRT entry. Additionally, the PE provides a frequent immediate table (FIT) for tracking occurrences of immediate values, and allocates IPRF registers for a given immediate value only when a count of occurrences of that immediate value exceeds a FIT threshold.

公开(公告)号：US11698789B2

公开(公告)日：2023-07-11

申请号：US17068253

申请日：2020-10-12

Applicant: Microsoft Technology Licensing, LLC

Inventor： Vignyan Reddy Kothinti Naresh ,  Rami Mohammad Al Sheikh ,  Shivam Priyadarshi ,  Arthur Perais

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3806 ,  G06F9/3861

Abstract: Restoring speculative history used for making speculative predictions for instructions processed in a processor. The processor can be configured to speculatively predict an outcome of a condition or predicate of a conditional control instruction before its condition is fully evaluated in execution. Predictions are made by the processor based on a history that is updated based on outcomes of past predictions. If a conditional control instruction is mispredicted in execution, the processor can perform a misprediction recovery by stalling the instruction pipeline, flushing younger instructions in the instruction pipeline back to the mispredicted conditional control instruction, and then re-fetching instructions in the correct instruction flow path for execution. The processor can be configured to restore entries of the speculative history associated with younger control independent (CI) conditional control instructions, so that younger fetched instructions that follow non-re-fetched CI instructions in misprediction recovery will use a more accurate speculative history.

公开(公告)号：US11334488B2

公开(公告)日：2022-05-17

申请号：US16898872

申请日：2020-06-11

Applicant: Microsoft Technology Licensing, LLC

Inventor： Rami Mohammad Al Sheikh ,  Arthur Perais ,  Michael Scott McIlvaine

IPC: G06F12/0871 ,  G06F12/0855 ,  G06F12/0895 ,  G06F12/1018 ,  G06F12/121

Abstract: A cache management circuit that includes a predictive adjustment circuit configured to predictively generate cache control information based on a cache hit-miss indicator and the retention ranks of accessed cache lines to improve cache efficiency is disclosed. The predictive adjustment circuit stores the cache control information persistently, independent of whether the data remains in cache memory. The stored cache control information is indicative of prior cache access activity for data from a memory address, which is indicative of the data's “usefulness.” Based on the cache control information, the predictive adjustment circuit controls generation of retention ranks for data in the cache lines when the data is inserted, accessed, and evicted. After the data has been evicted from the cache memory and is later accessed by a subsequent memory request, the persistently stored cache control information corresponding to that memory address increases the information available for determining the usefulness of data.

公开(公告)号：US11036512B2

公开(公告)日：2021-06-15

申请号：US16579161

申请日：2019-09-23

Applicant: Microsoft Technology Licensing, LLC

Inventor： Arthur Perais ,  Rodney Wayne Smith ,  Shivam Priyadarshi ,  Rami Mohammad Al Sheikh ,  Vignyan Reddy Kothinti Naresh

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor element in a processor-based system is configured to fetch one or more instructions associated with a program binary, where the one or more instructions include an instruction having an immediate operand. The processor element is configured to determine if the immediate operand is a reference to a wide immediate operand. In response to determining that the immediate operand is a reference to a wide immediate operand, the processor element is configured to retrieve the wide immediate operand from a common intermediate lookup table (CILT) in the program binary, where the immediate operand indexes the wide immediate operand in the CILT. The processor element is then configured to process the instruction having the immediate operand such that the immediate operand is replaced with the wide immediate operand from the CILT.