公开(公告)号：US20210064718A1

公开(公告)日：2021-03-04

申请号：US16559874

申请日：2019-09-04

申请人： Microsoft Technology Licensing, LLC

发明人： Janet L. Schneider ,  Kenneth Reneris ,  Mark G. Kupferschmidt ,  Brian L. Koehler ,  Adam J. Muff ,  Alexander L. Braun ,  Alison Ii

IPC分类号： G06F17/50 ,  G06F1/12 ,  H03K3/38

摘要： Superconducting circuit with virtual timing elements and related methods are described. A method includes specifying a superconducting circuit portion including a timing path comprising: (1) at least one logic gate to be implemented using Josephson junctions, (2) a first virtual timing element for defining a synchronization point along the timing path, and (3) a second virtual timing element for adding latency to the timing path. The method further includes synthesizing the superconducting circuit portion, where the synthesizing comprises treating the first virtual timing element as a first flip-flop and the second virtual timing element as a second flip-flop, where the first flip-flop is treated as being fixed in relation to the at least one logic gate along the timing path, but the second flip-flop is treated as being movable in relation to the at least one logic gate along the timing path.

公开(公告)号：US11030369B2

公开(公告)日：2021-06-08

申请号：US16559874

申请日：2019-09-04

申请人： Microsoft Technology Licensing, LLC

发明人： Janet L. Schneider ,  Kenneth Reneris ,  Mark G. Kupferschmidt ,  Brian L. Koehler ,  Adam J. Muff ,  Alexander L. Braun ,  Alison Ii

IPC分类号： G06F30/30 ,  G06F30/3323 ,  G06F30/3312 ,  G06F30/327 ,  G06F30/337 ,  G06F1/12 ,  H03K3/38 ,  G06F30/398 ,  G06F119/12 ,  G06F30/392 ,  G06F30/396 ,  G06F119/16

摘要： Superconducting circuit with virtual timing elements and related methods are described. A method includes specifying a superconducting circuit portion including a timing path comprising: (1) at least one logic gate to be implemented using Josephson junctions, (2) a first virtual timing element for defining a synchronization point along the timing path, and (3) a second virtual timing element for adding latency to the timing path. The method further includes synthesizing the superconducting circuit portion, where the synthesizing comprises treating the first virtual timing element as a first flip-flop and the second virtual timing element as a second flip-flop, where the first flip-flop is treated as being fixed in relation to the at least one logic gate along the timing path, but the second flip-flop is treated as being movable in relation to the at least one logic gate along the timing path.