公开(公告)号：US12037126B1

公开(公告)日：2024-07-16

申请号：US16568904

申请日：2019-09-12

申请人： SmartGridz, Inc.

发明人： Marija Ilic ,  Rupamathi Jaddivada

IPC分类号： B64D31/06 ,  B64D27/02 ,  B64D27/10 ,  B64D27/24 ,  F02C9/48 ,  G06F30/13 ,  G06F30/15 ,  G06F30/17 ,  G06F30/20 ,  G06F119/02 ,  G06F119/06 ,  G06F119/14 ,  G06F119/16

CPC分类号： B64D31/06 ,  B64D27/02 ,  B64D27/10 ,  B64D27/24 ,  F02C9/48 ,  B64D2027/026 ,  B64D2221/00 ,  G06F30/13 ,  G06F30/15 ,  G06F30/17 ,  G06F30/20 ,  G06F2119/02 ,  G06F2119/06 ,  G06F2119/14 ,  G06F2119/16

摘要： Disclosed herein is a fundamental modeling and control method in dynamic energy conversion and transfers in complex energy systems with multiple energy sources, fuel and electric. The multi-layered modeling enables efficient and stable operation through optimized coordination of engines and electric part of a hybrid turbo-electric distribution system (TeDP). A provable coordination of power and rate of change of power interactions between the components is done at the higher-system level. Advanced nonlinear control of components is disclosed to ensure that components meet power/rate of change of power commands given by the higher level. This method is used to demonstrate, for the first time, how rotor stall and surge instabilities in engines can be eliminated by controlling the electric generators and/or storage.

公开(公告)号：US11763054B2

公开(公告)日：2023-09-19

申请号：US17384483

申请日：2021-07-23

申请人： Imagination Technologies Limited

发明人： Sam Elliott ,  Robert McKerney ,  Max Freiburghaus

IPC分类号： G06F30/3323 ,  G06F119/16

CPC分类号： G06F30/3323 ,  G06F2119/16

摘要： Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

公开(公告)号：US11487925B1

公开(公告)日：2022-11-01

申请号：US17664677

申请日：2022-05-24

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Kun Weng

IPC分类号： G06F30/3308 ,  G06F30/333 ,  G06F30/367 ,  G06F30/398 ,  G06F119/16

摘要： A simulation method, apparatus, and a storage medium are provided. The simulation method includes: obtaining a pre-built local simulation model of a capacitor array region, wherein the local simulation model is configured to represent first simulation parameters of the capacitor array region; creating a local parameter netlist of a non-capacitor array region, wherein the local parameter netlist includes second simulation parameters of the non-capacitor array region; creating an overall parameter netlist of a peripheral region based on the local simulation model and the local parameter netlist, wherein the overall parameter netlist represents overall simulation parameters of the peripheral region, and the overall simulation parameters include the first simulation parameters and the second simulation parameters; and performing simulation on the peripheral region based on the overall parameter netlist.

公开(公告)号：US20240320407A1

公开(公告)日：2024-09-26

申请号：US18675048

申请日：2024-05-27

申请人： Imagination Technologies Limited

发明人： Sam Elliott

IPC分类号： G06F30/33 ,  G01R31/3183 ,  G06F30/3308 ,  G06F30/3323 ,  G06F30/337 ,  G06F111/12 ,  G06F115/02 ,  G06F119/16

CPC分类号： G06F30/33 ,  G01R31/318314 ,  G06F30/3323 ,  G06F30/337 ,  G06F30/3308 ,  G06F2111/12 ,  G06F2115/02 ,  G06F2119/16

摘要： A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.

公开(公告)号：US11900036B2

公开(公告)日：2024-02-13

申请号：US17382674

申请日：2021-07-22

申请人： Imagination Technologies Limited

发明人： Reinald Cruz

IPC分类号： G06F30/3323 ,  G06F119/16 ,  G06F119/12

CPC分类号： G06F30/3323 ,  G06F2119/12 ,  G06F2119/16

摘要： Methods and systems for verifying a property of an integrated circuit hardware design. The method includes formally verifying, using a formal verification tool, that the property is true for the hardware design under a constraint that an instantiation of the hardware design transitions to a quiescent state at a symbolic time.

公开(公告)号：US11157671B2

公开(公告)日：2021-10-26

申请号：US16920484

申请日：2020-07-03

申请人： Onespin Solutions GmbH

发明人： Peter Warkentin ,  Arun Chandrasekharan ,  Tobias Welp

IPC分类号： G06F30/3323 ,  G06F119/16

摘要： A method of checking equivalence between a first design comprising a shift register logic SRL chain and a second design comprising a memory block. The method comprises identifying an inductive invariant to replace the SRL chain or the memory block, and replacing the SRL chain and the memory block by a set of constraints, wherein the set of constraints state that the SRL chain and the memory block are equivalent for the checking of equivalence between the first design and the second design.

公开(公告)号：US11120184B2

公开(公告)日：2021-09-14

申请号：US16904077

申请日：2020-06-17

申请人： Synopsys, Inc.

发明人： Luca Gaetano Amaru ,  Jiong Luo ,  Patrick Vuillod

IPC分类号： G06F30/327 ,  G06F30/31 ,  G06F119/16

摘要： A system and method for SAT-sweeping is disclosed. According to one embodiment, a method includes determining gate classes by inputting simulation patterns to gates in an integrated circuit design, selecting a candidate gate based on an inverse topological ordering of the gates, and then selecting a driver gate belonging to the same gate class as the candidate gate. A SAT-solver is called based on the candidate gate and the driver gate to confirm equivalence. The candidate gate and the driver gate are then merged in the integrated circuit design.

公开(公告)号：US11017139B1

公开(公告)日：2021-05-25

申请号：US16828642

申请日：2020-03-24

申请人： Mentor Graphics Corporation

发明人： Pritam Roy ,  Sagar Chaki ,  Pankaj Chauhan

IPC分类号： G06F30/3323 ,  G06F30/3308 ,  G06F119/16

摘要： This application discloses a computing system to select a set of one or more values for control signals internal to multiple circuit designs, generate input stimulus for the circuit designs based, at least in part, on the selected set of values for the control signals, and simulate the circuit designs with the input stimulus, which configures the simulated values of the control signals internal to the circuits designs to the selected set of values. The computing system can perform an equivalence check on the circuit designs using results of the simulation. The computing system can select another set of values for the control signals, and determine that at least the other set of values for the control signals are not realizable during simulation with any input stimulus.

公开(公告)号：US11995386B2

公开(公告)日：2024-05-28

申请号：US18201070

申请日：2023-05-23

申请人： Imagination Technologies Limited

发明人： Sam Elliott

IPC分类号： G06F30/30 ,  G01R31/3183 ,  G06F30/33 ,  G06F30/3323 ,  G06F30/337 ,  G06F30/3308 ,  G06F111/12 ,  G06F115/02 ,  G06F119/16

CPC分类号： G06F30/33 ,  G01R31/318314 ,  G06F30/3323 ,  G06F30/337 ,  G06F30/3308 ,  G06F2111/12 ,  G06F2115/02 ,  G06F2119/16

摘要： A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.

公开(公告)号：US11900035B2

公开(公告)日：2024-02-13

申请号：US18176717

申请日：2023-03-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Chun Lo ,  Boh-Yi Huang ,  Chih-yuan Stephen Yu

IPC分类号： G06F30/30 ,  G06F30/33 ,  G06F119/16 ,  G06F119/12 ,  G06F111/04

CPC分类号： G06F30/33 ,  G06F2111/04 ,  G06F2119/12 ,  G06F2119/16

摘要： Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).