公开(公告)号：US12204408B2

公开(公告)日：2025-01-21

申请号：US18154164

申请日：2023-01-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar Agarwal ,  George Zacharias Chrysos ,  Oscar Rosell Martinez

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/14 ,  G06F12/0811

Abstract: Techniques of memory tiering include retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

公开(公告)号：US20220414001A1

公开(公告)日：2022-12-29

申请号：US17359104

申请日：2021-06-25

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar Agarwal ,  George Zacharias Chrysos ,  Oscar Rosell Martinez

IPC: G06F12/02 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0831 ,  G06F13/16

Abstract: Techniques of memory inclusivity management are disclosed herein. One example technique includes receiving a request from a core of the CPU to write a block of data corresponding to a first cacheline to a swap buffer at a memory. In response to the request, the method can include retrieving metadata corresponding to the first cacheline that includes a bit encoding a status value indicating whether the memory block at the memory currently contains data of the first cacheline or data corresponding to a second cacheline. The first and second cachelines alternately sharing the swap buffer at the memory. When the decoded status value indicates that the memory block at the first memory currently contains the data corresponding to the first cacheline, an instruction is transmitted to the memory controller to directly write the block of data to the memory block at the first memory.

公开(公告)号：US20230020131A1

公开(公告)日：2023-01-19

申请号：US17371422

申请日：2021-07-09

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar Agarwal ,  George Zacharias Chrysos ,  Oscar Rosell Martinez

IPC: G06F11/10 ,  G06F11/14 ,  G06F3/06 ,  G06F12/0811

Abstract: Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

公开(公告)号：US11599415B2

公开(公告)日：2023-03-07

申请号：US17371422

申请日：2021-07-09

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar Agarwal ,  George Zacharias Chrysos ,  Oscar Rosell Martinez

IPC: H03M13/00 ,  G06F11/10 ,  G06F11/14 ,  G06F3/06 ,  G06F12/0811

Abstract: Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

公开(公告)号：US11321171B1

公开(公告)日：2022-05-03

申请号：US17328891

申请日：2021-05-24

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar Agarwal ,  George Zacharias Chrysos ,  Oscar Rosell Martinez

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F3/06

Abstract: Techniques of memory operations management are disclosed herein. One example technique includes retrieving, from a first memory, data from a data portion and metadata from a metadata portion of the first memory upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first memory currently contains data corresponding to the system memory section in the received request. In response to determining that the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.