公开(公告)号：US12204408B2

公开(公告)日：2025-01-21

申请号：US18154164

申请日：2023-01-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar Agarwal ,  George Zacharias Chrysos ,  Oscar Rosell Martinez

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/14 ,  G06F12/0811

Abstract: Techniques of memory tiering include retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

公开(公告)号：US12039188B2

公开(公告)日：2024-07-16

申请号：US17894867

申请日：2022-08-24

Applicant: Microsoft Technology Licensing, LLC

Inventor： Lisa Ru-Feng Hsu ,  Aninda Manocha ,  Ishwar Agarwal ,  Daniel Sebastian Berger ,  Stanko Novakovic ,  Janaina Barreiro Gambaro Bueno ,  Vishal Soni

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0608 ,  G06F3/0673

Abstract: The present disclosure relates to systems, methods, and computer-readable media for tracking memory usage data on a memory controller system and providing a mechanism whereby one or multiple accessing agents (e.g., computing nodes, applications, virtual machines) can access memory usage data for a memory resource managed by a memory controller. Indeed, the systems described herein facilitate generation of and access to heatmaps having memory usage data thereon. The systems described herein describe features and functionality related to generating and maintaining the heatmaps as well as providing access to the heatmaps to a variety of accessing agents. This memory tracking and accessing is performed using low processing overhead while providing useful information to accessing agents in connection with memory resources managed by a memory controller.

公开(公告)号：US11860783B2

公开(公告)日：2024-01-02

申请号：US17735767

申请日：2022-05-03

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar Agarwal ,  Yevgeniy Bak ,  Lisa Ru-feng Hsu

IPC: G06F12/08 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/62

Abstract: Systems and methods related to direct swap caching with noisy neighbor mitigation and dynamic address range assignment are described. A system includes a host operating system (OS), configured to support a first set of tenants associated with a compute node, where the host OS has access to: (1) a first swappable range of memory addresses associated with a near memory and (2) a second swappable range of memory addresses associated with a far memory. The host OS is configured to allocate memory in a granular fashion such that each allocation of memory to a tenant includes memory addresses corresponding to a conflict set having a conflict set size. The conflict set includes a first conflicting region associated with the first swappable range of memory addresses with the near memory and a second conflicting region associated with the second swappable range of memory addresses with the far memory.

公开(公告)号：US12204909B2

公开(公告)日：2025-01-21

申请号：US18503869

申请日：2023-11-07

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar Agarwal ,  George Chrysos ,  Oscar Rosell Martinez ,  Yevgeniy Bak

IPC: G06F12/02 ,  G06F9/38 ,  G06F9/445 ,  G06F9/50 ,  G06F12/0815

Abstract: Systems and methods related to direct swap caching with zero line optimizations are described. A method for managing a system having a near memory and a far memory comprises receiving a request from a requestor to read a block of data that is either stored in the near memory or the far memory. The method includes analyzing a metadata portion associated with the block of data, the metadata portion comprising: both (1) information concerning whether the near memory contains the block of data or whether the far memory contains the block of data and (2) information concerning whether a data portion associated with the block of data is all zeros. The method further includes instead of retrieving the data portion from the far memory, synthesizing the data portion corresponding to the block of data to generate a synthesized data portion and transmitting the synthesized data portion to the requestor.

公开(公告)号：US11599415B2

公开(公告)日：2023-03-07

申请号：US17371422

申请日：2021-07-09

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar Agarwal ,  George Zacharias Chrysos ,  Oscar Rosell Martinez

IPC: H03M13/00 ,  G06F11/10 ,  G06F11/14 ,  G06F3/06 ,  G06F12/0811

Abstract: Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

公开(公告)号：US11321171B1

公开(公告)日：2022-05-03

申请号：US17328891

申请日：2021-05-24

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar Agarwal ,  George Zacharias Chrysos ,  Oscar Rosell Martinez

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F3/06

Abstract: Techniques of memory operations management are disclosed herein. One example technique includes retrieving, from a first memory, data from a data portion and metadata from a metadata portion of the first memory upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first memory currently contains data corresponding to the system memory section in the received request. In response to determining that the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

公开(公告)号：US12189764B2

公开(公告)日：2025-01-07

申请号：US17828903

申请日：2022-05-31

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar Agarwal ,  Stefan Saroiu ,  Alastair Wolman ,  Daniel Sebastian Berger

IPC: G11C8/20 ,  G06F21/55 ,  G11C11/406

Abstract: The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may track activations of row addresses within a memory hardware (e.g., a DRAM device) and determine whether a pattern of activations is indicative of a row hammer attack. This is determined using a counting mode for corresponding memory sub-banks. Where a likely row hammer attack is detected, the memory controller may activate a sampling mode (rather than the counting mode) for a particular sub-bank to identify which of the row addresses should be refreshed on the memory hardware. The implementations described herein provide a low computational cost alternative to heavy-handed detection mechanisms that require access to significant computing resources to accurately detect and mitigate row hammer attacks.

公开(公告)号：US11989416B2

公开(公告)日：2024-05-21

申请号：US18049224

申请日：2022-10-24

Applicant: Microsoft Technology Licensing, LLC

Inventor： Siamak Tavallaei ,  Ishwar Agarwal

IPC: G06F13/16 ,  G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0673 ,  G06F13/1668

Abstract: A computing device includes a system-on-a-chip. The computing device comprises a network interface controller (NIC) that hosts a plurality of virtual functions and physical functions. Two or more compute nodes are coupled to the NIC. Each compute node is configured to operate a plurality of Virtual Machines (VMs). Each VM is configured to operate in conjunction with a virtual function via a virtual function driver. A dedicated VM operates in conjunction with a virtual NIC using a physical function hosted by the NIC via a physical function driver hosted by the compute node. The computing device further comprises a fabric manager configured to own a physical function of the NIC, to bind virtual functions hosted by the NIC to individual compute nodes, and to pool I/O devices across the two or more compute nodes.

公开(公告)号：US12182620B2

公开(公告)日：2024-12-31

申请号：US17689553

申请日：2022-03-08

Applicant: Microsoft Technology Licensing, LLC

Inventor： Ishwar Agarwal

IPC: G06F12/08 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0891

Abstract: Systems and methods related to integrated memory pooling and direct swap caching are described. A system includes a compute node comprising a local memory and a pooled memory. The system further includes a host operating system (OS) having initial access to: (1) a first swappable range of memory addresses associated with the local memory and a non-swappable range of memory addresses associated with the local memory, and (2) a second swappable range of memory addresses associated with the pooled memory. The system further includes a data-mover offload engine configured to perform a cleanup operation, including: (1) restore a state of any memory content swapped-out from a memory location within the first swappable range of memory addresses to the pooled memory, and (2) move from the local memory any memory content swapped-in from a memory location within the second swappable range of memory addresses back out to the pooled memory.

公开(公告)号：US11853798B2

公开(公告)日：2023-12-26

申请号：US17011805

申请日：2020-09-03

Applicant: Microsoft Technology Licensing, LLC

Inventor： Siamak Tavallaei ,  Vishal Soni ,  Ishwar Agarwal

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/30 ,  G06F9/4401 ,  G06F12/02

CPC classification number: G06F9/5016 ,  G06F9/30101 ,  G06F9/4411 ,  G06F9/467 ,  G06F9/5083 ,  G06F12/0238 ,  G06F2209/508 ,  G06F2209/5011 ,  G06F2209/5022

Abstract: Examples are disclosed that relate to a disaggregated memory pool. One example provides a memory system comprising a memory controller and memory attached to the memory controller and forming at least a portion of a disaggregated memory pool, the disaggregated memory pool including a plurality of slices that are each dynamically assigned to a respective compute node. The memory system is configured to receive a request to adjust an assignment of the memory pool to a requesting compute node, where the portion of the memory pool includes an unassigned slice that can satisfy the request, assign at least part of the unassigned portion to the requesting compute node, and where the portion of the memory pool does not include an unassigned slice that can satisfy the request, cause a request to be directed to another compute node to free at least one slice to the such compute node.