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    METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE PERMUTE CONTROLS WITH LEADING ZERO COUNT FUNCTIONALITY
    5.
    发明申请
    METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE PERMUTE CONTROLS WITH LEADING ZERO COUNT FUNCTIONALITY 有权
    方法，设备，说明和逻辑提供带有领先零点功能的PTE控制

    公开(公告)号：US20140189309A1

    公开(公告)日：2014-07-03

    申请号：US13731008

    申请日：2012-12-29

    申请人： Christopher J. Hughes ,  Mikhail Plotnikov ,  Andrey Naraikin ,  Robert Valentine

    发明人： Christopher J. Hughes ,  Mikhail Plotnikov ,  Andrey Naraikin ,  Robert Valentine

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3834

    摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.

    摘要翻译： 说明和逻辑提供带有零计数功能的SIMD置换控制。 一些实施例包括具有多个数据字段的寄存器的处理器，每个数据字段用于存储第二多个位。 目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储对于相应数据字段设置为零的最重要连续位数的计数。 响应于对向量前导零计数指令进行解码，执行单元对寄存器中的每个数据字段计数设置为零的最高有效连续位的数目，并将计数存储在第一目的地寄存器的相应数据字段中。 向量前导零计数指令可用于生成与该组置换控制一起使用的置换控制和完成掩码，以解决采集修改散射SIMD操作中的依赖关系。

    LOOP VECTORIZATION METHODS AND APPARATUS
    6.
    发明申请
    LOOP VECTORIZATION METHODS AND APPARATUS 有权
    LOOP VECTORIZATION方法和装置

    公开(公告)号：US20140095850A1

    公开(公告)日：2014-04-03

    申请号：US13994549

    申请日：2012-09-28

    申请人： Mikhail Plotnikov ,  Andrey Naraikin ,  Christopher J. Hughes

    发明人： Mikhail Plotnikov ,  Andrey Naraikin ,  Christopher J. Hughes

    IPC分类号： G06F9/38

    CPC分类号： G06F9/38 ,  G06F8/4441 ,  G06F8/452 ,  G06F9/30018 ,  G06F9/30036 ,  G06F15/8084

    摘要： Loop vectorization methods and apparatus are disclosed. An example method includes generating a first control mask for a set of iterations of a loop by evaluating a condition of the loop, wherein generating the first control mask includes setting a bit of the control mask to a first value when the condition indicates that an operation of the loop is to be executed, and setting the bit of the first control mask to a second value when the condition indicates that the operation of the loop is to be bypassed. The example method also includes compressing indexes corresponding to the first set of iterations of the loop according to the first control mask.

    摘要翻译： 公开了环向量化方法和装置。 一个示例性方法包括：通过评估循环的条件来生成循环的一组迭代的第一控制掩码，其中产生所述第一控制掩码包括当所述条件指示操作时将所述控制掩码的位设置为第一值 并且当条件指示要循环的操作被绕过时，将第一控制掩码的位设置为第二值。 示例性方法还包括根据第一控制掩码压缩对应于循环的第一组迭代的索引。

    COLLAPSING OF MULTIPLE NESTED LOOPS, METHODS AND INSTRUCTIONS
    10.
    发明申请
    COLLAPSING OF MULTIPLE NESTED LOOPS, METHODS AND INSTRUCTIONS 有权
    多个嵌套的鞋子的收缩，方法和指导

    公开(公告)号：US20140189287A1

    公开(公告)日：2014-07-03

    申请号：US13728506

    申请日：2012-12-27

    申请人： Mikhail Plotnikov ,  Andrey Naraikin ,  Elmoustapha Ould-Ahmed-Vall

    发明人： Mikhail Plotnikov ,  Andrey Naraikin ,  Elmoustapha Ould-Ahmed-Vall

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/3016 ,  G06F9/325

    摘要： In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明涉及一种包括解码逻辑以接收多维循环计数器更新指令并将多维循环计数器更新指令解码为至少一个解码指令的处理器，以及执行逻辑 所述至少一个解码指令将与所述多维循环计数器更新指令相关联的第一操作数的至少一个循环计数器值更新第一量。 还公开了使用这样的指令折叠环的方法。 描述和要求保护其他实施例。