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公开(公告)号：US20140189287A1
公开(公告)日：2014-07-03
申请号：US13728506
申请日：2012-12-27
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30065 , G06F9/3016 , G06F9/325
摘要： In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明涉及一种包括解码逻辑以接收多维循环计数器更新指令并将多维循环计数器更新指令解码为至少一个解码指令的处理器，以及执行逻辑 所述至少一个解码指令将与所述多维循环计数器更新指令相关联的第一操作数的至少一个循环计数器值更新第一量。 还公开了使用这样的指令折叠环的方法。 描述和要求保护其他实施例。
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2.发明申请UNIQUE PACKED DATA ELEMENT IDENTIFICATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开独特的包装数据元素识别处理器，方法，系统和说明公开(公告)号：US20140351567A1
公开(公告)日：2014-11-27
申请号：US13977686
申请日：2011-12-30
IPC分类号： G06F9/30
CPC分类号： G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/4552
摘要： A method of an aspect includes receiving a unique packed data element identification instruction. The unique packed data element identification instruction indicates a source packed data having a plurality of packed data elements and indicates a destination storage location. A unique packed data element identification result is stored in the destination storage location in response to the unique packed data element identification instruction. The unique packed data element identification result indicates which of the plurality of the packed data elements are unique in the source packed data. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一种方面的方法包括接收唯一的打包数据元素识别指令。 独特的打包数据元素识别指令指示具有多个打包数据元素的源打包数据，并且指示目的地存储位置。 响应于唯一的打包数据元素识别指令，唯一的打包数据元素识别结果被存储在目的地存储位置中。 独特的打包数据元素识别结果指示多个打包数据元素中的哪一个在源打包数据中是唯一的。 公开了其它方法，装置，系统和指令。
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公开(公告)号：US20140188961A1
公开(公告)日：2014-07-03
申请号：US13728439
申请日：2012-12-27
IPC分类号： G06F17/11
摘要： In an embodiment a method of vectorizing a collapsed multi-nested loop includes executing, in a vector unit of a processor, the collapsed loop to obtain a vector of offsets, including for each of a plurality of iterations, calculating a scalar offset into a multi-dimensional data structure, storing the scalar offset in a data element of a first vector register, and updating a loop counter value of a multi-dimensional loop counter vector. In turn, a plurality of data elements are loaded from the multi-dimensional data structure using a base value and indexes from the vector of offsets, at least one computation is performed on the loaded plurality of data elements to obtain a plurality of results, and the plurality of results are stored into the multi-dimensional data structure using the base value and the indexes from the vector of offsets. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，向量化折叠多嵌套循环的方法包括在处理器的向量单元中执行折叠循环以获得偏移向量，包括对于多个迭代中的每一个，将标量偏移计算为多 将标量偏移存储在第一向量寄存器的数据元素中，以及更新多维循环计数器向量的循环计数器值。 接着，使用基本值从多维数据结构中加载多个数据元素，并从偏移矢量进行索引，对被加载的多个数据元素进行至少一次计算以获得多个结果，以及 使用基本值和来自偏移矢量的索引将多个结果存储到多维数据结构中。 描述和要求保护其他实施例。
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公开(公告)号：US20130339678A1
公开(公告)日：2013-12-19
申请号：US13997998
申请日：2011-12-23
申请人： Mikhail Plotnikov , Andrey Naraikan , Elmoustapha Ould-Ahmed-vall , Robert Valentine , Bret L. Toll , Jesus Corbal
发明人： Mikhail Plotnikov , Andrey Naraikan , Elmoustapha Ould-Ahmed-vall , Robert Valentine , Bret L. Toll , Jesus Corbal
IPC分类号： G06F9/30
CPC分类号： G06F9/3013 , G06F7/764 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30036
摘要： A method is described that includes reading a first read mask from a first register. The method also includes reading a first vector operand from a second register or memory location. The method also includes applying the read mask against the first vector operand to produce a set of elements for operation. The method also includes performing an operation of the set elements. The method also includes creating an output vector by producing multiple instances of the operation's result. The method also includes reading a first write mask from a third register, the first write mask being different than the first read mask. The method also includes applying the write mask against the output vector to create a resultant vector. The method also includes writing the resultant vector to a destination register.
摘要翻译： 描述了一种包括从第一寄存器读取第一读取掩码的方法。 该方法还包括从第二寄存器或存储器位置读取第一向量操作数。 该方法还包括对第一向量操作数应用读取掩码以产生用于操作的一组元素。 该方法还包括执行设定元件的操作。 该方法还包括通过产生操作结果的多个实例来创建输出向量。 该方法还包括从第三寄存器读取第一写掩码，第一写掩码不同于第一读掩码。 该方法还包括针对输出向量应用写掩码以产生合成矢量。 该方法还包括将结果矢量写入目的地寄存器。
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公开(公告)号：US20140201497A1
公开(公告)日：2014-07-17
申请号：US13976004
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3555 , G06F9/3001 , G06F9/30036 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/355 , G06F9/3802 , G06F9/3893
摘要： An apparatus is described having functional unit logic circuitry. The functional unit logic circuitry has a first register to store a first input vector operand having an element for each dimension of a multi-dimensional data structure. Each element of the first vector operand specifying the size of its respective dimension. The functional unit has a second register to store a second input vector operand specifying coordinates of a particular segment of the multi-dimensional structure. The functional unit also has logic circuitry to calculate an address offset for the particular segment relative to an address of an origin segment of the multi-dimensional structure.
摘要翻译： 描述了具有功能单元逻辑电路的装置。 功能单元逻辑电路具有第一寄存器以存储具有用于多维数据结构的每个维度的元素的第一输入向量操作数。 第一个向量操作数的每个元素指定其相应维度的大小。 功能单元具有第二寄存器，用于存储指定多维结构的特定段的坐标的第二输入向量操作数。 功能单元还具有逻辑电路，用于相对于多维结构的原点片段的地址计算特定片段的地址偏移。
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公开(公告)号：US09507593B2
公开(公告)日：2016-11-29
申请号：US13976004
申请日：2011-12-23
CPC分类号： G06F9/3555 , G06F9/3001 , G06F9/30036 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/355 , G06F9/3802 , G06F9/3893
摘要： An apparatus is described having functional unit logic circuitry. The functional unit logic circuitry has a first register to store a first input vector operand having an element for each dimension of a multi-dimensional data structure. Each element of the first vector operand specifying the size of its respective dimension. The functional unit has a second register to store a second input vector operand specifying coordinates of a particular segment of the multi-dimensional structure. The functional unit also has logic circuitry to calculate an address offset for the particular segment relative to an address of an origin segment of the multi-dimensional structure.
摘要翻译： 描述了具有功能单元逻辑电路的装置。 功能单元逻辑电路具有第一寄存器以存储具有用于多维数据结构的每个维度的元素的第一输入向量操作数。 第一个向量操作数的每个元素指定其相应维度的大小。 功能单元具有第二寄存器，用于存储指定多维结构的特定段的坐标的第二输入向量操作数。 功能单元还具有逻辑电路，用于相对于多维结构的原点片段的地址计算特定片段的地址偏移。
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公开(公告)号：US20180246722A1
公开(公告)日：2018-08-30
申请号：US15445577
申请日：2017-02-28
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30032 , G06F9/30043 , G06F9/30138 , G06F9/30145 , G06F9/30196 , G06F9/3455
摘要： A method performed by a processor includes receiving an instruction. The instruction indicating a source operand, indicating a stride, indicating at least one set of strided data element positions out of all sets of strided data element positions for the indicated stride, and indicating at least one destination packed data register. The method also includes storing, in response to the instruction, for each of the indicated at least one set of strided data element positions, a corresponding result packed data operand, in a corresponding destination packed data register of the processor. Each result packed data operand including a plurality of data elements, which are from the corresponding indicated set of strided data element positions of the source operand. The strided data element positions of the set are separated from one another by integer multiples of the indicated stride. Other methods, processors, systems, and machine readable media are also disclosed.
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公开(公告)号：US09489196B2
公开(公告)日：2016-11-08
申请号：US13997998
申请日：2011-12-23
申请人： Mikhail Plotnikov , Andrey Naraikan , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Bret L. Toll , Jesus Corbal
发明人： Mikhail Plotnikov , Andrey Naraikan , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Bret L. Toll , Jesus Corbal
CPC分类号： G06F9/3013 , G06F7/764 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30036
摘要： A method is described that includes reading a first read mask from a first register. The method also includes reading a first vector operand from a second register or memory location. The method also includes applying the read mask against the first vector operand to produce a set of elements for operation. The method also includes performing an operation of the set elements. The method also includes creating an output vector by producing multiple instances of the operation's result. The method also includes reading a first write mask from a third register, the first write mask being different than the first read mask. The method also includes applying the write mask against the output vector to create a resultant vector. The method also includes writing the resultant vector to a destination register.
摘要翻译： 描述了一种包括从第一寄存器读取第一读取掩码的方法。 该方法还包括从第二寄存器或存储器位置读取第一向量操作数。 该方法还包括对第一向量操作数应用读取掩码以产生用于操作的一组元素。 该方法还包括执行设定元件的操作。 该方法还包括通过产生操作结果的多个实例来创建输出向量。 该方法还包括从第三寄存器读取第一写掩码，第一写掩码不同于第一读掩码。 该方法还包括针对输出向量应用写掩码以产生合成矢量。 该方法还包括将结果矢量写入目的地寄存器。
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公开(公告)号：US10162639B2
公开(公告)日：2018-12-25
申请号：US15912498
申请日：2018-03-05
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
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10.发明授权公开(公告)号：US10162638B2
公开(公告)日：2018-12-25
申请号：US15912486
申请日：2018-03-05
摘要： Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
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