公开(公告)号：US20070005945A1

公开(公告)日：2007-01-04

申请号：US11515971

申请日：2006-09-06

申请人： Mikio Hondou

发明人： Mikio Hondou

IPC分类号： G06F15/00

CPC分类号： G06F9/3848

摘要： A branch prediction apparatus reads out a branch history table 15 by an index calculated by the output of a branch history register 14 containing a plurality of the latest branch result of a branch instruction. The branch prediction apparatus comprises frequency detection units 18-20 for detecting the appearance frequency of a branch instruction with a different address and data width modification units 16 and 21 for modifying the number of valid bits of the branch history register, based on the detected appearance frequency. Even a program in which a branch result strongly depends on the latest branch history or even a program having a plenty of branch instructions can maintain high prediction accuracy with a small capacity of the branch history table.

摘要翻译： 分支预测装置通过由包含分支指令的多个最新分支结果的分支历史寄存器14的输出计算的索引读出分支历史表15。 分支预测装置包括频率检测单元18-20，用于基于检测到的外观来检测具有不同地址的分支指令的出现频率和用于修改分支历史寄存器的有效位数的数据宽度修改单元16和21 频率。 即使分支结果强烈依赖于最新分支历史的程序，甚至具有大量分支指令的程序，也可以以分支历史表的小容量来保持高预测精度。

公开(公告)号：US06760836B2

公开(公告)日：2004-07-06

申请号：US09797734

申请日：2001-03-05

申请人： Mikio Hondou

发明人： Mikio Hondou

IPC分类号： G06F930

CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/384

摘要： An instruction issuing device comprises a plurality of issue controlling circuits which run in parallel, and perform a control for preferentially issuing an instruction to a particular arithmetic unit. An optimum issue controlling circuit is selected according to the empty quantity of instruction slots for each arithmetic unit or a result of learning of the number of previously issued instructions, and an issue destination is determined based on the direction of the selected circuit.

摘要翻译： 指令发布装置包括并行运行的多个发行控制电路，并且执行用于优先向特定算术单元发出指令的控制。 根据每个运算单元的指示槽的空闲量或先前发出的指令的数量的学习结果来选择最佳的问题控制电路，并且基于所选择的电路的方向来确定发布目的地。

公开(公告)号：US08281112B2

公开(公告)日：2012-10-02

申请号：US12338245

申请日：2008-12-18

申请人： Toshio Yoshida ,  Mikio Hondou

发明人： Toshio Yoshida ,  Mikio Hondou

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/30101

摘要： A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into the extended register, extends the subsequent instruction based on the instruction extension information.

摘要翻译： 处理单元具有扩展寄存器，可以设置指示扩展指令的指令扩展信息。 一种操作单元，当指令扩展信息被设置为扩展寄存器时，执行将指令扩展信息写入扩展寄存器的第一指令之后的后续指令，根据指令扩展信息来扩展后续指令。

公开(公告)号：US07827393B2

公开(公告)日：2010-11-02

申请号：US11515971

申请日：2006-09-06

申请人： Mikio Hondou

发明人： Mikio Hondou

IPC分类号： G06F9/00

CPC分类号： G06F9/3848

摘要： A branch prediction apparatus reads out a branch history table 15 by an index calculated by the output of a branch history register 14 containing a plurality of the latest branch result of a branch instruction. The branch prediction apparatus comprises frequency detection units 18-20 for detecting the appearance frequency of a branch instruction with a different address and data width modification units 16 and 21 for modifying the number of valid bits of the branch history register, based on the detected appearance frequency. Even a program in which a branch result strongly depends on the latest branch history or even a program having a plenty of branch instructions can maintain high prediction accuracy with a small capacity of the branch history table.

摘要翻译： 分支预测装置通过由包含分支指令的多个最新分支结果的分支历史寄存器14的输出计算的索引读出分支历史表15。 分支预测装置包括频率检测单元18-20，用于基于检测到的外观来检测具有不同地址的分支指令的出现频率和用于修改分支历史寄存器的有效位数的数据宽度修改单元16和21 频率。 即使分支结果强烈依赖于最新分支历史的程序，甚至具有大量分支指令的程序，也可以以分支历史表的小容量来保持高预测精度。

公开(公告)号：US08560784B2

公开(公告)日：2013-10-15

申请号：US13238190

申请日：2011-09-21

申请人： Noriyuki Takahashi ,  Mikio Hondou

发明人： Noriyuki Takahashi ,  Mikio Hondou

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/1642 ,  G06F13/1663

摘要： A priority control register 104 dynamically controls the internal transition state based on the issuability state of a memory request obtained in the memory request issuability signal generation unit 106 and retaining state of the memory request in the REQ_BUF 102 obtained by each of determination circuits 105 #2 through #5. Thus, the jump control of the priorities corresponding to the access regulation of the DRAM module 109 can be realized.

摘要翻译： 优先级控制寄存器104基于在存储器请求发布信号生成单元106中获得的存储器请求的可发行性状态来动态地控制内部转换状态，并且在由每个确定电路105＃2获得的REQ_BUF 102中保持存储器请求的状态 通过＃5。 因此，可以实现与DRAM模块109的访问调节相对应的优先级的跳转控制。

公开(公告)号：US20120079216A1

公开(公告)日：2012-03-29

申请号：US13238190

申请日：2011-09-21

申请人： Noriyuki TAKAHASHI ,  Mikio Hondou

发明人： Noriyuki TAKAHASHI ,  Mikio Hondou

IPC分类号： G06F12/00

CPC分类号： G06F13/1642 ,  G06F13/1663

摘要： A priority control register 104 dynamically controls the internal transition state based on the issuability state of a memory request obtained in the memory request issuability signal generation unit 106 and retaining state of the memory request in the REQ_BUF 102 obtained by each of determination circuits 105 #2 through #5. Thus, the jump control of the priorities corresponding to the access regulation of the DRAM module 109 can be realized.

摘要翻译： 优先级控制寄存器104基于在存储器请求发布信号生成单元106中获得的存储器请求的可发行性状态来动态地控制内部转换状态，并且在由每个确定电路105＃2获得的REQ_BUF 102中保持存储器请求的状态 通过＃5。 因此，可以实现与DRAM模块109的访问调节相对应的优先级的跳转控制。

公开(公告)号：US08074029B2

公开(公告)日：2011-12-06

申请号：US12200369

申请日：2008-08-28

申请人： Mikio Hondou

发明人： Mikio Hondou

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0897 ,  G06F2212/6028

摘要： A processor equipped with a pre-fetch function comprises: first layer cache memory having a first line size; second layer cache memory that is on the under layer of the first layer cache memory and that has a second line size different from the first line size; and a pre-fetch control unit for issuing a pre-fetch request from the first layer cache memory to the second layer cache memory so as to pre-fetch a block equivalent to the first line size for each second line size.

摘要翻译： 配备有预取功能的处理器包括：具有第一行大小的第一层高速缓冲存储器; 第二层高速缓存存储器，位于第一层高速缓冲存储器的下层上，并且具有与第一行大小不同的第二行大小; 以及预取控制单元，用于从第一层高速缓冲存储器向第二层高速缓存存储器发出预取请求，以便为每个第二行大小预取相当于第一行大小的块。

公开(公告)号：US20090172367A1

公开(公告)日：2009-07-02

申请号：US12338245

申请日：2008-12-18

申请人： Toshio Yoshida ,  Mikio Hondou

发明人： Toshio Yoshida ,  Mikio Hondou

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/30101

摘要： A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into the extended register, extends the subsequent instruction based on the instruction extension information.

摘要翻译： 处理单元具有扩展寄存器，可以设置指示扩展指令的指令扩展信息。 一种操作单元，当指令扩展信息被设置为扩展寄存器时，执行将指令扩展信息写入扩展寄存器的第一指令之后的后续指令，根据指令扩展信息来扩展后续指令。

公开(公告)号：US08655935B2

公开(公告)日：2014-02-18

申请号：US12047782

申请日：2008-03-13

申请人： Mikio Hondou ,  Ryuji Kan ,  Toshio Yoshida

发明人： Mikio Hondou ,  Ryuji Kan ,  Toshio Yoshida

IPC分类号： G06F1/02

CPC分类号： G06F7/548 ,  G06F1/02 ,  G06F7/483 ,  G06F7/5443

摘要： A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.

摘要翻译： 一种处理装置，包括存储操作数数据的寄存器，读取存储在寄存器中的操作数数据的寄存器数据读取部，存储存储泰勒级数运算系数数据的系数表的系数表组存储部，读取 使用泰勒级数的度数信息和系数表识别信息的系数表组存储部分的泰勒级数系数数据和使用由系数数据读取部分读取的系数数据执行泰勒级数操作的浮点乘法器 ，从寄存器读取的数据。

公开(公告)号：US08583872B2

公开(公告)日：2013-11-12

申请号：US12193888

申请日：2008-08-19

申请人： Shuji Yamamura ,  Mikio Hondou ,  Iwao Yamazaki ,  Toshio Yoshida

发明人： Shuji Yamamura ,  Mikio Hondou ,  Iwao Yamazaki ,  Toshio Yoshida

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/127

摘要： A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.

摘要翻译： 具有根据设定的关联系统操作的扇区功能的高速缓存存储器，并且执行高速缓存操作以以与在发生高速缓存未命中时确定的替换高速缓存方式相对应的高速缓存方式来替换高速缓存块中的数据包括：存储 与由存储器访问请求指定的高速缓存块中的每个缓存路径相关联的扇区ID信息; 根据附加到存储器访问请求的扇区ID信息和存储的扇区ID信息，确定高速缓存未命中的替换方式候选; 从替代方式候选人中选择和输出替代方式; 以及将与由存储器访问请求指定的高速缓存块中的每个高速缓存路径相关联地存储的扇区ID信息更新到附加到存储器访问请求的扇区ID信息。