公开(公告)号：US20090103368A1

公开(公告)日：2009-04-23

申请号：US12339153

申请日：2008-12-19

申请人： Mikio OGAWA ,  Norihiro Fujita ,  Hiroshi Nakamura

发明人： Mikio OGAWA ,  Norihiro Fujita ,  Hiroshi Nakamura

IPC分类号： G11C11/34 ,  H01L29/788

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28

摘要： A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.

摘要翻译： 半导体存储器件包括存储单元阵列和读出放大器电路。 存储单元阵列包括连接到存储器单元的位线，该存储器单元可操作以存储第一逻辑数据和小区电流中比第一逻辑小的第二逻辑数据。 感测放大器电路具有用于钳位位线电压的钳位晶体管。 感测放大器电路用于通过钳位晶体管和位线检测所选存储单元中的数据。 当将控制电压施加到钳位晶体管的栅极时，感测放大器电路用于在至少两个第一和第二读取周期中从所选存储单元读取数据。 在第一和第二读取周期中，不同的控制电压施加到钳位晶体管的栅极。

公开(公告)号：US07486562B2

公开(公告)日：2009-02-03

申请号：US11194608

申请日：2005-08-02

申请人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

发明人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

IPC分类号： G11C11/34

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28

摘要： A semiconductor memory device comprises a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.

摘要翻译： 半导体存储器件包括存储单元阵列和读出放大器电路。 存储单元阵列包括连接到存储器单元的位线，该存储器单元可操作以存储第一逻辑数据和小区电流中比第一逻辑小的第二逻辑数据。 感测放大器电路具有用于钳位位线电压的钳位晶体管。 感测放大器电路用于通过钳位晶体管和位线检测所选存储单元中的数据。 当将控制电压施加到钳位晶体管的栅极时，感测放大器电路用于在至少两个第一和第二读取周期中从所选存储单元读取数据。 在第一和第二读取周期中，不同的控制电压施加到钳位晶体管的栅极。

公开(公告)号：US20100165744A1

公开(公告)日：2010-07-01

申请号：US12723057

申请日：2010-03-12

申请人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

发明人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

IPC分类号： G11C16/06 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28

摘要： A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.

摘要翻译： 半导体存储器件包括存储单元阵列和读出放大器电路。 存储单元阵列包括连接到存储器单元的位线，该存储器单元可操作以存储第一逻辑数据和小区电流中比第一逻辑小的第二逻辑数据。 感测放大器电路具有用于钳位位线电压的钳位晶体管。 感测放大器电路用于通过钳位晶体管和位线检测所选存储单元中的数据。 当将控制电压施加到钳位晶体管的栅极时，感测放大器电路用于在至少两个第一和第二读取周期中从所选存储单元读取数据。 在第一和第二读取周期中，不同的控制电压施加到钳位晶体管的栅极。

公开(公告)号：US20060034140A1

公开(公告)日：2006-02-16

申请号：US11194608

申请日：2005-08-02

申请人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

发明人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

IPC分类号： G11C8/00

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28

摘要： A semiconductor memory device comprises a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.

公开(公告)号：US08004903B2

公开(公告)日：2011-08-23

申请号：US12723057

申请日：2010-03-12

申请人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

发明人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

IPC分类号： G11C11/34

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28

摘要： A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.

摘要翻译： 半导体存储器件包括存储单元阵列和读出放大器电路。 存储单元阵列包括连接到存储器单元的位线，该存储器单元可操作以存储第一逻辑数据和小区电流中比第一逻辑小的第二逻辑数据。 感测放大器电路具有用于钳位位线电压的钳位晶体管。 感测放大器电路用于通过钳位晶体管和位线检测所选存储单元中的数据。 当将控制电压施加到钳位晶体管的栅极时，感测放大器电路用于在至少两个第一和第二读取周期中从所选存储单元读取数据。 在第一和第二读取周期中，不同的控制电压施加到钳位晶体管的栅极。

公开(公告)号：US07701777B2

公开(公告)日：2010-04-20

申请号：US12339153

申请日：2008-12-19

申请人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

发明人： Mikio Ogawa ,  Norihiro Fujita ,  Hiroshi Nakamura

IPC分类号： G11C11/34

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/28

摘要： A semiconductor memory device includes a memory cell array and a sense amp circuit. The memory cell array includes bit lines connected to memory cells operative to store first logic data and second logic data smaller in cell current than the first logic. The sense amp circuit has a clamp transistor operative to clamp a bit line voltage. The sense amp circuit is operative to detect data in a selected memory cell via the clamp transistor and the bit line. The sense amp circuit is operative to read data from the selected memory cell in at least the two of first and second read cycles while a control voltage is applied to a gate of the clamp transistor. Different control voltages are applied to the gate of the clamp transistor in the first and second read cycles.

摘要翻译： 半导体存储器件包括存储单元阵列和读出放大器电路。 存储单元阵列包括连接到存储器单元的位线，该存储器单元可操作以存储第一逻辑数据和小区电流中比第一逻辑小的第二逻辑数据。 感测放大器电路具有用于钳位位线电压的钳位晶体管。 感测放大器电路用于通过钳位晶体管和位线检测所选存储单元中的数据。 当将控制电压施加到钳位晶体管的栅极时，感测放大器电路用于在至少两个第一和第二读取周期中从所选存储单元读取数据。 在第一和第二读取周期中，不同的控制电压施加到钳位晶体管的栅极。

公开(公告)号：US07486569B2

公开(公告)日：2009-02-03

申请号：US11609646

申请日：2006-12-12

申请人： Norihiro Fujita ,  Hiroyuki Nagashima ,  Hiroshi Nakamura

发明人： Norihiro Fujita ,  Hiroyuki Nagashima ,  Hiroshi Nakamura

IPC分类号： G11C7/10

CPC分类号： G11C16/10

摘要： A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.

摘要翻译： 非易失性半导体存储器包括：第一半导体芯片，其上安装有第一存储器; 安装有第二存储器的第二半导体芯片; 其中，在作为复制目的地的第二存储器中，在启动将读取使能操作识别为可启用操作的命令之后执行读取使能操作，以及作为第一存储器的源的第一存储器的数据 复制，被复制到第二个内存。

公开(公告)号：US20060133155A1

公开(公告)日：2006-06-22

申请号：US11293376

申请日：2005-12-05

申请人： Norihiro Fujita ,  Hiroshi Nakamura

发明人： Norihiro Fujita ,  Hiroshi Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/107 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3445

摘要： A nonvolatile semiconductor memory device comprises memory cell array constituted of a plurality of memory blocks which electrically rewritable memory cells are arranged, before erasing data of all of said memory cells in the selected memory block in a plurality of said memory blocks, preprogram is performed to shift all threshold voltages of all of said memory cells in said selected memory blocks to positive.

摘要翻译： 非易失性半导体存储器件包括由多个存储单元构成的存储单元阵列，所述存储单元阵列在擦除多个所述存储器块中所选择的存储器块中的所有存储单元的数据之前，布置电可重写存储单元， 将所选择的存储器块中的所有存储单元的所有阈值电压移位为正。

公开(公告)号：US20100238727A1

公开(公告)日：2010-09-23

申请号：US12788614

申请日：2010-05-27

申请人： Norihiro FUJITA ,  Hiroyuki Nagashima ,  Hiroshi Nakamura

发明人： Norihiro FUJITA ,  Hiroyuki Nagashima ,  Hiroshi Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.

摘要翻译： 非易失性半导体存储器包括：第一半导体芯片，其上安装有第一存储器; 安装有第二存储器的第二半导体芯片; 其中，在作为复制目的地的第二存储器中，在启动将读取使能操作识别为可启用操作的命令之后执行读取使能操作，以及作为第一存储器的源的第一存储器的数据 复制，被复制到第二个内存。

公开(公告)号：US20070133281A1

公开(公告)日：2007-06-14

申请号：US11609646

申请日：2006-12-12

申请人： Norihiro FUJITA ,  Hiroyuki Nagashima ,  Hiroshi Nakamura

发明人： Norihiro FUJITA ,  Hiroyuki Nagashima ,  Hiroshi Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.

摘要翻译： 非易失性半导体存储器包括：第一半导体芯片，其上安装有第一存储器; 安装有第二存储器的第二半导体芯片; 其中，在作为复制目的地的第二存储器中，在启动将读取使能操作识别为可启用操作的命令之后执行读取使能操作，以及作为第一存储器的源的第一存储器的数据 复制，被复制到第二个内存。