公开(公告)号：US12046290B2

公开(公告)日：2024-07-23

申请号：US17125459

申请日：2020-12-17

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC分类号： G11C16/10 ,  G06N3/065 ,  G11C16/16

CPC分类号： G11C16/107 ,  G06N3/065 ,  G11C16/16

摘要： Numerous embodiments of programming, verifying, and reading systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells can be programmed and verified with extreme precision to hold one of N different values. During a read operation, the system determines which of the N different values is stored in a selected cell.

公开(公告)号：US20190196727A1

公开(公告)日：2019-06-27

申请号：US16289173

申请日：2019-02-28

申请人： SK hynix Inc.

发明人： Se-Hyun KIM

IPC分类号： G06F3/06 ,  G06F11/10 ,  G11C16/34 ,  G06F11/07 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26

CPC分类号： G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/1048 ,  G11C16/107 ,  G11C16/26 ,  G11C16/3404 ,  G11C29/82

摘要： A memory system includes: a memory device including a plurality of memory blocks; and a controller suitable for selecting one or more first memory blocks based on a predetermined condition among the plurality of the memory blocks in a booting section, and increasing a read reclaim count value of one or more second memory blocks among the one or more first memory blocks for which a number of failed bits of read data exceeds a predetermined threshold.

公开(公告)号：US20190074283A1

公开(公告)日：2019-03-07

申请号：US16052238

申请日：2018-08-01

申请人： Toshiba Memory Corporation

发明人： Takehiko AMAKI ,  Yoshihisa Kojima ,  Toshikatsu Hida ,  Marie Sia ,  Riki Suzuki ,  Shohei Asami

IPC分类号： H01L27/11556 ,  G11C16/10 ,  G11C16/08

CPC分类号： H01L27/11556 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/16 ,  G11C16/26 ,  H01L27/1157 ,  H01L27/11582

摘要： According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

公开(公告)号：US20190066801A1

公开(公告)日：2019-02-28

申请号：US16116806

申请日：2018-08-29

申请人： Western Digital Technologies, Inc.

发明人： Ajith Kumar BATTAJE ,  Mahesh Mandya VARDHAMANAIAH ,  Ashwin NARASIMHA ,  Sandeep SHARMA

IPC分类号： G11C16/16 ,  G11C29/44 ,  G11C29/34 ,  G11C29/52 ,  G11C16/10 ,  G11C29/42 ,  G11C29/04

CPC分类号： G11C16/16 ,  G11C16/107 ,  G11C29/34 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/4402

摘要： A sequence of contiguous pages in an erase block in a non-volatile memory device is programmed and erased. Next, all of the pages in the erase block are programmed with data. Then, the data is read back and verified to determine whether there is an error in the data. When there is an error in the data, then the last page in the sequence is identified as being unstable. If there is no error in the data, then the last page in that sequence is identified as being stable. Thus, the recorded information identifies a point of instability in the erase block. Instabilities can be stabilized by performing additional writes to fill the partially filled word line.

公开(公告)号：US20180294277A1

公开(公告)日：2018-10-11

申请号：US15844188

申请日：2017-12-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Chang-Bum Kim ,  Sunghoon Kim

IPC分类号： H01L27/11582 ,  G11C16/08 ,  G11C16/10 ,  G11C16/04 ,  H01L27/02 ,  H01L27/1157 ,  H01L27/11575 ,  G11C5/02 ,  G11C8/10

CPC分类号： H01L27/11582 ,  G11C5/025 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  H01L27/0207 ,  H01L27/1157 ,  H01L27/11575

摘要： A three-dimensional semiconductor memory device includes a cell string vertically extending from a top surface of a substrate and having first and second cell transistors, first and second word lines connected to gate electrodes of the first and second cell transistors respectively, a first pass transistor connecting the first word line to a row decoder, and a second pass transistor connecting the second word line to the row decoder. The first pass transistor includes a plurality of first sub-transistors connected in parallel between the first word line and the row decoder.

公开(公告)号：US10074433B1

公开(公告)日：2018-09-11

申请号：US15786604

申请日：2017-10-18

申请人： PHISON ELECTRONICS CORP.

发明人： Yu-Cheng Hsu ,  Wei Lin ,  Yu-Siang Yang

IPC分类号： G11C7/00 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C7/10

CPC分类号： G11C16/107 ,  G11C7/1006 ,  G11C7/1045 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

摘要： A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming unit of a first physical programming unit group among a plurality of physical programming unit groups; writing a second data into a second physical programming unit of a second physical programming unit group among the plurality of physical programming unit groups; encoding the first data and the second data to generate an encoded data; and writing the encoded data into a third physical programming unit group among the plurality of physical programming unit groups.

公开(公告)号：US20180204621A1

公开(公告)日：2018-07-19

申请号：US15919155

申请日：2018-03-12

申请人： Samsung Electronics Co., Ltd.

发明人： Yoon Kim ,  Dong-chan Kim ,  Ji-sang Lee

IPC分类号： G11C16/14 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56

CPC分类号： G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/107 ,  G11C16/349

摘要： A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.

公开(公告)号：US20180053543A1

公开(公告)日：2018-02-22

申请号：US15613736

申请日：2017-06-05

申请人： SK hynix Inc.

发明人： Hee Youl LEE

IPC分类号： G11C11/408

CPC分类号： G11C11/4085 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/107 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459

摘要： Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device having improved reliability includes a memory cell array including memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform a program operation on a word line selected from among the plurality of word lines, and control logic configured to control the peripheral circuit so that, when the selected word line is a reference word line during the program operation, a partial erase operation is performed on memory cells included in a memory cell group corresponding to the reference word line.

公开(公告)号：US09799397B2

公开(公告)日：2017-10-24

申请号：US15437715

申请日：2017-02-21

申请人： Apple Inc.

发明人： Micha Anholt ,  Naftali Sommer

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/10

CPC分类号： G11C11/5628 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/26 ,  G11C16/3427

摘要： A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally inverting the encoded data prior to storing the encoded data in the memory cells. The encoded data is read from the memory cells, and inner code decoding is applied to the read encoded data to produce a decoding result. At least part of the read data is conditionally inverted, depending on the decoding result of the inner code.

公开(公告)号：US09773559B2

公开(公告)日：2017-09-26

申请号：US14585147

申请日：2014-12-29

申请人： SK hynix Inc.

发明人： Sung Lae Oh

IPC分类号： G11C7/10 ,  G11C16/10 ,  G11C8/10 ,  G11C7/06

CPC分类号： G11C16/107 ,  G11C7/06 ,  G11C7/10 ,  G11C8/10 ,  G11C16/10

摘要： A flash memory device includes a first page buffer, a second page buffer neighboring the first page buffer, a source-pick-up region disposed between the first page buffer and the second page buffer, and a source line extending in a direction. The source line includes a first portion that corresponds to the first page buffer and a second portion that corresponds to the second page buffer. A first resistance value of the first portion is substantially the same as a second resistance value of the second portion.