METHOD AND APPARATUS FOR SELECTING PRE-CODING VECTORS
    1.
    发明申请
    METHOD AND APPARATUS FOR SELECTING PRE-CODING VECTORS 有权
    用于选择预编码向量的方法和装置

    公开(公告)号:US20100027713A1

    公开(公告)日:2010-02-04

    申请号:US12528096

    申请日:2008-02-22

    IPC分类号: H04L25/03

    摘要: To optimize the selection of pre-coding vectors in a multi-user MIMO system, the present invention provides a method for selecting pre-coding vectors in a base station, comprising the steps of: transmitting a plurality of pilot signals without being precoded to the plurality of terminals; receiving a plurality of feedback signals from the plurality of terminals, wherein at least one feedback signal includes a plurality of recommended pre-coding vector information and a plurality of channel status information, and each of the channel status information corresponds to a recommended pre-coding vector information; generate a pre-coding codebook based on the plurality feedback signals, wherein at least one pre-coding vector in the pre-coding codebook is determined based on a correlation coefficient between at least two recommended pre-coding vectors; and performing a transmission operation using the pre-coding codebook. Through considering the correlation among pre-coding vectors and different channel status information corresponding to different pre-coding vectors, be used to extend the selection range of pre-coding vectors and improve the total transmission rate of the whole system and system capacity.

    摘要翻译: 为了优化多用户MIMO系统中的预编码向量的选择,本发明提供了一种用于在基站中选择预编码向量的方法,包括以下步骤:发送多个导频信号而不经预编码到 多个终端; 从所述多个终端接收多个反馈信号,其中至少一个反馈信号包括多个推荐的预编码矢量信息和多个信道状态信息,并且每个信道状态信息对应于推荐的预编码 矢量信息; 基于所述多个反馈信号生成预编码码本,其中,所述预编码码本中的至少一个预编码矢量基于至少两个推荐的预编码矢量之间的相关系数来确定; 以及使用所述预编码码本执行发送操作。 通过考虑预编码矢量与对应于不同预编码矢量的不同信道状态信息之间的相关性,可用于扩展预编码矢量的选择范围,提高整个系统的总传输速率和系统容量。

    "> High speed PLD
    2.
    发明授权
    High speed PLD "AND" array with separate nonvolatile memory 失效
    高速PLD“AND”阵列具有单独的非易失性存储器

    公开(公告)号:US5760603A

    公开(公告)日:1998-06-02

    申请号:US729079

    申请日:1996-10-10

    申请人: Shidong Zhou

    发明人: Shidong Zhou

    IPC分类号: H03K19/177 H03K7/38

    CPC分类号: H03K19/17704

    摘要: The invention is a unique high speed Programmable Logic Device ("PLD") AND array with separate nonvolatile memory. The invention utilizes a separate nonvolatile memory to isolate the effect of nonvolatile transistors from the proper operation of the PLD AND array. The invention also results in a substantial increase in the amount of current flowing through transistors charging and discharging the PLD AND array bit lines. This in turn significantly increases the speed of the invention's PLD AND array. Moreover, the invention makes the current charging or discharging the PLD AND array bit lines more predictable. These advantages of the present invention are achieved by a nonvolatile memory that is separate from the AND array itself and also by utilizing NMOS transistors in the AND array instead of using the prior art nonvolatile transistors such as EEPROM transistors in the AND array.

    摘要翻译: 本发明是具有独立的非易失性存储器的独特的高速可编程逻辑器件(“PLD”)AND阵列。 本发明利用单独的非易失性存储器来隔离非易失性晶体管对PLD AND阵列的正常操作的影响。 本发明还导致流过晶体管的电流量的大量增加,该晶体管对PLD AND阵列位线进行充电和放电。 这又大大增加了本发明的PLD AND阵列的速度。 此外,本发明使得PLD AND阵列位线的电流充电或放电更可预测。 本发明的这些优点通过与AND阵列本身分离并且还通过在AND阵列中利用NMOS晶体管而不是使用现有技术的非易失性晶体管例如AND阵列中的EEPROM晶体管来实现。

    E-fuse read circuit with dual comparators
    3.
    发明授权
    E-fuse read circuit with dual comparators 有权
    电子熔丝读取电路与双比较器

    公开(公告)号:US07936582B1

    公开(公告)日:2011-05-03

    申请号:US12051806

    申请日:2008-03-19

    IPC分类号: G11C17/00 G11C7/00

    CPC分类号: G11C17/16 G11C7/04 G11C17/18

    摘要: An integrated circuit has an E-fuse sense circuit configured to produce a READ voltage according to a fuse resistance of an E-fuse during a READ operation. The integrated circuit also has a reference sense circuit configured to produce a reference voltage according to a reference resistance of an on-chip reference resistor during the READ operation. The reference sense circuit replicates the E-fuse sense circuit. The E-fuse sense circuit and the reference sense circuit are coupled to a comparator that produces a bit value according to a difference between the READ voltage and the reference voltage.

    摘要翻译: 集成电路具有E熔丝感测电路,其被配置为在读取操作期间根据电熔丝的熔丝电阻产生读取电压。 集成电路还具有参考感测电路,其被配置为在读取操作期间根据片上参考电阻器的参考电阻产生参考电压。 参考感测电路复制了E熔丝检测电路。 E熔丝检测电路和参考检测电路耦合到比较器,该比较器根据读取电压和参考电压之间的差产生位值。

    Method and apparatus for providing a combination differential driver
    4.
    发明授权
    Method and apparatus for providing a combination differential driver 有权
    用于提供组合差分驱动器的方法和装置

    公开(公告)号:US07656198B1

    公开(公告)日:2010-02-02

    申请号:US11999091

    申请日:2007-12-03

    IPC分类号: H03K19/094

    CPC分类号: H03K19/018528

    摘要: In one embodiment, an integrated device is disclosed. For example, in one embodiment of the present invention, a device comprises a logic control, and a combination differential driver coupled to the logic control, wherein the logic control receives a control signal for configuring the combination differential driver as a Low Voltage Differential Signaling (LVDS) driver or as a Transition Minimized Differential Signaling (TMDS) driver.

    摘要翻译: 在一个实施例中,公开了一种集成装置。 例如,在本发明的一个实施例中,设备包括逻辑控制和耦合到逻辑控制的组合差分驱动器,其中逻辑控制接收用于将组合差分驱动器配置为低电压差分信号的控制信号( LVDS)驱动器或作为转换最小化差分信号(TMDS)驱动程序。