公开(公告)号：US07936582B1

公开(公告)日：2011-05-03

申请号：US12051806

申请日：2008-03-19

申请人： Shidong Zhou ,  Gubo Huang

发明人： Shidong Zhou ,  Gubo Huang

IPC分类号： G11C17/00 ,  G11C7/00

CPC分类号： G11C17/16 ,  G11C7/04 ,  G11C17/18

摘要： An integrated circuit has an E-fuse sense circuit configured to produce a READ voltage according to a fuse resistance of an E-fuse during a READ operation. The integrated circuit also has a reference sense circuit configured to produce a reference voltage according to a reference resistance of an on-chip reference resistor during the READ operation. The reference sense circuit replicates the E-fuse sense circuit. The E-fuse sense circuit and the reference sense circuit are coupled to a comparator that produces a bit value according to a difference between the READ voltage and the reference voltage.

摘要翻译： 集成电路具有E熔丝感测电路，其被配置为在读取操作期间根据电熔丝的熔丝电阻产生读取电压。 集成电路还具有参考感测电路，其被配置为在读取操作期间根据片上参考电阻器的参考电阻产生参考电压。 参考感测电路复制了E熔丝检测电路。 E熔丝检测电路和参考检测电路耦合到比较器，该比较器根据读取电压和参考电压之间的差产生位值。

公开(公告)号：US07236004B1

公开(公告)日：2007-06-26

申请号：US11238780

申请日：2005-09-29

申请人： Shi-dong Zhou ,  Gubo Huang

发明人： Shi-dong Zhou ,  Gubo Huang

IPC分类号： H03K19/003

CPC分类号： H04L25/0272

摘要： Apparatus and method for providing reference voltages for differential signaling with tracking of output differential voltage relative to output offset voltage are described. A swing reference voltage, an offset reference voltage, a swing feedback voltage, and an offset feedback voltage are obtained. Differences between pairs of these voltages are differentially amplified to produce first and second bias voltages. Pull-up and pull-down voltages are driven partially responsive to the first bias voltage and the second bias voltage to provide first and second control voltages. The first control voltage may be provided to a first resistance for the driving of the first pull-up and pull-down voltages. The second control voltage may be provided to a second resistance for the driving of the second pull-up and pull-down voltages. The first control voltage and the second control voltage may be provided to a third resistance.

摘要翻译： 描述了用于为差分信号提供参考电压的设备和方法，其具有相对于输出偏移电压的输出差分电压的跟踪。 获得摆幅参考电压，偏移参考电压，摆动反馈电压和偏移反馈电压。 这些电压对之间的差异被差分放大以产生第一和第二偏置电压。 部分地响应于第一偏置电压和第二偏置电压驱动上拉和下拉电压以提供第一和第二控制电压。 可以将第一控制电压提供给用于驱动第一上拉和下拉电压的第一电阻。 可以将第二控制电压提供给用于驱动第二上拉和下拉电压的第二电阻。 第一控制电压和第二控制电压可以被提供给第三电阻。

公开(公告)号：US07161396B1

公开(公告)日：2007-01-09

申请号：US10644156

申请日：2003-08-20

申请人： Shi-Dong Zhou ,  Gubo Huang

发明人： Shi-Dong Zhou ,  Gubo Huang

IPC分类号： H03L7/00

CPC分类号： H03K17/223

摘要： A power-on reset circuit for generating a reset signal for an associated IC device includes a pull-up resistor connected between a supply voltage and a tracking node, a pull-down transistor connected between the tracking node and ground potential, and a voltage divider circuit connected between the supply voltage and ground potential. The voltage divider circuit has a first ratioed voltage node coupled to the gate of the pull-down transistor. For some embodiments, the voltage divider circuit includes a first resistor connected between the voltage supply and the first ratioed voltage node, a second resistor connected between the first ratioed voltage node and a second ratioed voltage node, a third resistor connected between the second ratioed voltage node and ground potential, and a shunt transistor connected between the second ratioed voltage node and ground potential has a gate responsive to the reset signal.

摘要翻译： 用于产生关联IC器件的复位信号的上电复位电路包括连接在电源电压和跟踪节点之间的上拉电阻，连接在跟踪节点和接地电位之间的下拉晶体管，以及分压器 电路连接在电源电压和地电位之间。 分压器电路具有耦合到下拉晶体管的栅极的第一比例电压节点。 对于一些实施例，分压器电路包括连接在电压源和第一比较电压节点之间的第一电阻器，连接在第一比较电压节点和第二比值电压节点之间的第二电阻器，连接在第二比率电压节点 连接在第二比较电压节点和地电位之间的并联晶体管具有响应于复位信号的栅极。

公开(公告)号：US06628151B1

公开(公告)日：2003-09-30

申请号：US10136115

申请日：2002-04-30

申请人： Shi-dong Zhou ,  Gubo Huang ,  Andy T. Nguyen

发明人： Shi-dong Zhou ,  Gubo Huang ,  Andy T. Nguyen

IPC分类号： H03K406

CPC分类号： H03K17/223 ,  H03K4/50

摘要： A self-regulating ramp up circuit generates a high voltage signal having a slow, smooth ramp up and reduced process and temperature variation. The circuit uses a resistor and a capacitor to control the rate at which the output signal changes state. In one embodiment, an enable signal operating at a low voltage level is shifted to the desired high voltage level using a level shifter. The resulting value is inverted using an inverter operating at the high voltage level and having a resistor in the pulldown path. The circuit output node is coupled to the output node of the inverter through a capacitor, and to the high voltage power supply through a pullup gated by the output node of the inverter. In some embodiments, the ramp up circuit forms a portion of a programmable logic device (PLD), and the capacitor and/or resistor have programmable capacitance/resistance values.

摘要翻译： 自调节斜坡电路产生具有缓慢，平滑的上升和降低的工艺和温度变化的高电压信号。 电路使用电阻和电容来控制输出信号变化的速率。 在一个实施例中，使用电平移位器将在低电压电平下工作的使能信号转换到期望的高电压电平。 使用在高电压电平下工作并在下拉路径中具有电阻器的逆变器来反转所得到的值。 电路输出节点通过电容器耦合到逆变器的输出节点，并通过由逆变器的输出节点选通的上拉电路连接到高压电源。 在一些实施例中，斜坡上升电路形成可编程逻辑器件（PLD）的一部分，并且电容器和/或电阻器具有可编程的电容/电阻值。

公开(公告)号：US08793419B1

公开(公告)日：2014-07-29

申请号：US13286495

申请日：2011-11-01

申请人： Kwok W. Yeung ,  Meng-Kun Lee ,  Gubo Huang

发明人： Kwok W. Yeung ,  Meng-Kun Lee ,  Gubo Huang

IPC分类号： G06F13/00 ,  G06F13/14 ,  G06F11/00 ,  G06F11/16

CPC分类号： G06F13/1668 ,  G06F12/0246 ,  G06F13/385 ,  G06F2212/7207 ,  G06F2213/3802

摘要： A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface.

摘要翻译： 第二控制器经由接口从第一控制器通信。 存储器还通过接口从第一控制器传送。 第一个控制器被配置为接口上的主控器，第二个控制器和存储器被配置为接口上的目标。

公开(公告)号：US06496044B1

公开(公告)日：2002-12-17

申请号：US10016950

申请日：2001-12-13

申请人： Hy V. Nguyen ,  Gubo Huang ,  Andy T. Nguyen

发明人： Hy V. Nguyen ,  Gubo Huang ,  Andy T. Nguyen

IPC分类号： H03K300

CPC分类号： H03K19/01721 ,  H03K19/00315

摘要： Output circuits that provide compatibility with various input and output voltage levels without sacrificing performance. A pull-up on an output terminal is gated by an internal node, and the invention encompasses various circuits and means for placing a data input signal on this internal node. One embodiment includes a level shifter on the data input path, while also providing an alternative path through the output circuit that bypasses the level shifter. When the input data value goes high, the alternative path quickly places an attenuated high value on the internal node. The level shifter then becomes active and raises the voltage on the internal node to the output power high level, ensuring that the output pull-up is completely off.

摘要翻译： 输出电路，提供与各种输入和输出电压电平的兼容性，而不会牺牲性能。 输出端子上的上拉由内部节点门控，本发明包括用于在该内部节点上放置数据输入信号的各种电路和装置。 一个实施例包括数据输入路径上的电平移位器，同时还提供绕过电平移位器的输出电路的替代路径。 当输入数据值变高时，替代路径会快速地将衰减的高值放在内部节点上。 电平移位器然后变为有效，并将内部节点上的电压提高到输出功率高电平，确保输出上拉完全关闭。

公开(公告)号：US06504401B1

公开(公告)日：2003-01-07

申请号：US10006548

申请日：2001-11-30

申请人： Gubo Huang ,  Hy V. Nguyen ,  Shankar Lakkapragada

发明人： Gubo Huang ,  Hy V. Nguyen ,  Shankar Lakkapragada

IPC分类号： H03K190185

CPC分类号： H03K19/00315

摘要： A low-voltage output circuit configurably providing a bus-hold function and a weak pull-up function, while having only transitory leakage current through the circuit regardless of the voltage level on the pad. Thus, the output circuit can be used in low-voltage devices that interface with higher-voltage devices without paying the penalty of increased leakage current. One embodiment of the invention includes a circuit output node coupled to a configurable weak pull-up circuit, a configurable bus hold circuit, and a configurable leakage prevention circuit. The configurable circuits are controlled by configuration signals that determine which circuits are active. One embodiment is implemented as a portion of a programmable logic device (PLD), and the configuration signals are programmed into configuration memory cells as part of the configuration of the PLD.

摘要翻译： 低压输出电路可配置提供总线保持功能和弱上拉功能，同时只有短暂的漏电流通过电路，无论焊盘上的电压电平如何。 因此，输出电路可以用于与高电压器件接口的低电压器件，而不会增加漏电流的损失。 本发明的一个实施例包括耦合到可配置弱上拉电路的电路输出节点，可配置总线保持电路和可配置的防漏电路。 可配置电路由确定哪些电路有效的配置信号控制。 一个实施例被实现为可编程逻辑器件（PLD）的一部分，并且配置信号被编程到配置存储器单元中，作为PLD的配置的一部分。

公开(公告)号：US06476638B1

公开(公告)日：2002-11-05

申请号：US09876676

申请日：2001-06-07

申请人： Shi dong Zhou ,  Gubo Huang

发明人： Shi dong Zhou ,  Gubo Huang

IPC分类号： H03K190185

CPC分类号： H03K19/018585 ,  H03K3/3565

摘要： An input driver circuit for accommodating a plurality of input/output voltage standards is provided. The input driver circuit employs an adjustable trip point that can be calibrated for multiple input voltage standards. The adjustable trip point is provided by a trigger circuit. A control circuit determines whether the trigger circuit is on or off by comparing a configuration input thereof with a reference power supply input thereof. When the trigger circuit is on, the trip point is active during a low to high transition of the signal input.

摘要翻译： 提供一种用于容纳多个输入/输出电压标准的输入驱动电路。 输入驱动电路采用可调整的跳变点，可针对多个输入电压标准进行校准。 可调跳闸点由触发电路提供。 控制电路通过将其配置输入与其参考电源输入进行比较来确定触发电路是开或关。 当触发电路接通时，在信号输入的低电平到高电平跳变期间，跳变点有效。

公开(公告)号：US07479805B1

公开(公告)日：2009-01-20

申请号：US11888790

申请日：2007-08-01

申请人： Shi-dong Zhou ,  Gubo Huang ,  Andy T. Nguyen ,  Ronald L. Cline

发明人： Shi-dong Zhou ,  Gubo Huang ,  Andy T. Nguyen ,  Ronald L. Cline

IPC分类号： H03K19/0175

CPC分类号： H04L25/028 ,  H04L25/0264 ,  H04L25/0272 ,  H04L25/0288

摘要： A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.

摘要翻译： 可编程差分信号系统包括可编程偏置发生器和多个输入/输出模块。 可编程偏置发生器被可操作地耦合以基于多个差分信号约定中的一个的期望信号特性产生第一全局偏置信号和第二全局信号。 多个输入/输出模块可操作地耦合以在差分信令和单端信令之间进行转换，其中基于第一和第二全局偏置信号来调节差分信令的实际信号特性以基本上等于期望的信号特性。

公开(公告)号：US07279982B1

公开(公告)日：2007-10-09

申请号：US11089848

申请日：2005-03-24

申请人： Shi-dong Zhou ,  Andy T. Nguyen ,  Gubo Huang

发明人： Shi-dong Zhou ,  Andy T. Nguyen ,  Gubo Huang

IPC分类号： H03F3/04

CPC分类号： H03F3/45475 ,  H03F2203/45138 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0292

摘要： Low current differential signal/swing I/O interfaces and techniques can be implemented. An output interface converts input data signals to differential current signals for transmission over transmission lines. When the differential current signals are received by an input interface, they are converted to differential voltage signals and appropriately amplified.

摘要翻译： 可实现低电流差分信号/摆幅I / O接口和技术。 输出接口将输入数据信号转换为差分电流信号，以通过传输线传输。 当差分电流信号由输入接口接收时，它们被转换成差分电压信号并被适当放大。