公开(公告)号：US20090004797A1

公开(公告)日：2009-01-01

申请号：US11965706

申请日：2007-12-27

Applicant: Min-Suk LEE

Inventor： Min-Suk LEE

IPC: H01L21/336

CPC classification number: H01L29/66666 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

Abstract: A method of fabricating a semiconductor device includes forming a plurality of pillars which are arranged on a substrate in a first direction and a second direction that intersects the first direction, thereby forming a resulting structure, forming a capping layer on the resulting structure including the pillars, removing the capping layer formed on the substrate between the pillars to expose the substrate between the pillars, thereby forming a resulting structure, forming a metal layer on the resulting structure, forming a silicide layer on the exposed substrate between the pillars by applying a first heat treatment to the metal layer, removing a non-reacted silicide layer, and forming an isolation trench in the substrate which is between rows of the pillars arranged in the first direction and is under the silicide layer to define bit lines which surround the pillars and are extended to the first direction.

Abstract translation: 制造半导体器件的方法包括：在与第一方向相交的第一方向和第二方向上形成布置在基板上的多个柱，从而形成所得到的结构，在所得到的结构上形成覆盖层，所述结构包括柱 去除在支柱之间形成在衬底上的覆盖层，以暴露柱之间的衬底，由此形成所得结构，在所得结构上形成金属层，通过施加第一衬底在所述柱之间的暴露衬底上形成硅化物层 对金属层进行热处理，去除未反应的硅化物层，以及在衬底中形成隔离沟槽，所述衬底位于沿着第一方向布置的柱的行之间，并且位于硅化物层下方以限定围绕柱的位线， 延伸到第一个方向。

公开(公告)号：US20090004813A1

公开(公告)日：2009-01-01

申请号：US11951957

申请日：2007-12-06

Applicant: Min-Suk LEE

Inventor： Min-Suk LEE

IPC: H01L21/76

CPC classification number: H01L27/10823 ,  H01L27/10885 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method and system are provided for fabricating a semiconductor device that includes a vertical channel transistor. An area of a buried bit line is uniformly formed by an isolation trench. The width of the isolation trench is adjusted by controlling the thickness of spacers. Consequently, the area of the buried bit line is relatively large compared with that of a typical buried bit line. The resistance characteristics of the buried bit line are improved and stability and reliability of the semiconductor device are ensured.

Abstract translation: 提供了一种用于制造包括垂直沟道晶体管的半导体器件的方法和系统。 掩埋位线的区域由隔离沟槽均匀地形成。 通过控制间隔物的厚度来调节隔离沟槽的宽度。 因此，与典型的掩埋位线相比，埋入位线的面积相对较大。 提高了掩埋位线的电阻特性，确保了半导体器件的稳定性和可靠性。

公开(公告)号：US20090004855A1

公开(公告)日：2009-01-01

申请号：US11965966

申请日：2007-12-28

Applicant: Min-Suk LEE ,  Won-Kyu KIM

Inventor： Min-Suk LEE ,  Won-Kyu KIM

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76895 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method of fabricating a semiconductor device, the method includes forming gate patterns on a substrate, recessing the substrate between the gate patterns, thereby forming a first resulting structure including recesses, forming a gate spacer layer on an entire surface of the first resulting structure including the gate patterns, etching the gate spacer layer at a bottom of the recess, and forming a plug on the recess, thereby forming a second resulting structure including the plug.

Abstract translation: 一种制造半导体器件的方法，该方法包括在衬底上形成栅极图案，使衬底在栅极图案之间凹陷，从而形成包括凹槽的第一结果结构，在第一结果结构的整个表面上形成栅极间隔层，包括 栅极图案，在凹部的底部蚀刻栅极间隔层，并且在凹部上形成插塞，从而形成包括插头的第二结果结构。