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公开(公告)号：US20090273868A1
公开(公告)日：2009-11-05
申请号：US12116745
申请日：2008-05-07
IPC分类号： H02H9/04
CPC分类号： H01L27/0262 , H01L29/7436 , H01L29/866
摘要： A transient voltage suppressor and a method for protecting against surge and electrostatic discharge events. A semiconductor substrate of a first conductivity type has gate and anode regions of a second conductivity type formed therein. A PN junction diode is formed from a portion of the gate region and the semiconductor substrate. A cathode is formed adjacent to another portion of the gate region. A thyristor is formed from the cathode, the gate region, the substrate, and the anode region. Zener diodes are formed from other portions of the gate region and the semiconductor substrate. A second Zener diode has a breakdown voltage that is greater than a breakdown voltage of a first Zener diode and that is greater than a breakover voltage of the thyristor. The first Zener diode protects against a surge event and the second Zener diode protects against an electrostatic discharge event.
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公开(公告)号：US08339758B2
公开(公告)日：2012-12-25
申请号：US12113843
申请日：2008-05-01
IPC分类号： H02H9/04
CPC分类号： H01L27/0262 , H01L29/7436 , H01L29/866
摘要： A transient voltage suppressor and a method for protecting against surge and electrostatic discharge events. A semiconductor substrate of a first conductivity type has gate and anode regions of a second conductivity type formed therein. A PN junction diode is formed from a portion of the gate region and the semiconductor substrate. A cathode is formed adjacent to another portion of the gate region. A thyristor is formed from the cathode, the gate region, the substrate, and the anode region. Zener diodes are formed from other portions of the gate region and the semiconductor substrate. A second Zener diode has a breakdown voltage that is greater than a breakdown voltage of a first Zener diode and that is greater than a breakover voltage of the thyristor. The first Zener diode protects against a surge event and the second Zener diode protects against an electrostatic discharge event.
摘要翻译： 瞬态电压抑制器和防止浪涌和静电放电事件的方法。 第一导电类型的半导体衬底具有形成在其中的第二导电类型的栅极和阳极区域。 PN结二极管由栅极区域和半导体衬底的一部分形成。 阴极与栅极区域的另一部分相邻地形成。 从阴极，栅极区域，衬底和阳极区域形成晶闸管。 齐纳二极管由栅极区域和半导体衬底的其它部分形成。 第二齐纳二极管具有大于第一齐纳二极管的击穿电压并且大于晶闸管的跳变电压的击穿电压。 第一个齐纳二极管可防止浪涌事件，第二个齐纳二极管可防止静电放电事件。
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公开(公告)号：US20090273876A1
公开(公告)日：2009-11-05
申请号：US12113843
申请日：2008-05-01
IPC分类号： H02H9/04
CPC分类号： H01L27/0262 , H01L29/7436 , H01L29/866
摘要： A transient voltage suppressor and a method for protecting against surge and electrostatic discharge events. A semiconductor substrate of a first conductivity type has gate and anode regions of a second conductivity type formed therein. A PN junction diode is formed from a portion of the gate region and the semiconductor substrate. A cathode is formed adjacent to another portion of the gate region. A thyristor is formed from the cathode, the gate region, the substrate, and the anode region. Zener diodes are formed from other portions of the gate region and the semiconductor substrate. A second Zener diode has a breakdown voltage that is greater than a breakdown voltage of a first Zener diode and that is greater than a breakover voltage of the thyristor. The first Zener diode protects against a surge event and the second Zener diode protects against an electrostatic discharge event.
摘要翻译： 瞬态电压抑制器和防止浪涌和静电放电事件的方法。 第一导电类型的半导体衬底具有形成在其中的第二导电类型的栅极和阳极区域。 PN结二极管由栅极区域和半导体衬底的一部分形成。 阴极与栅极区域的另一部分相邻地形成。 从阴极，栅极区域，衬底和阳极区域形成晶闸管。 齐纳二极管由栅极区域和半导体衬底的其它部分形成。 第二齐纳二极管具有大于第一齐纳二极管的击穿电压并且大于晶闸管的跳变电压的击穿电压。 第一个齐纳二极管可防止浪涌事件，第二个齐纳二极管可防止静电放电事件。
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公开(公告)号：US08093133B2
公开(公告)日：2012-01-10
申请号：US12098369
申请日：2008-04-04
IPC分类号： H01L21/20
CPC分类号： H01L29/87 , H01L29/747 , H01L29/866
摘要： Transient voltage suppressor and method for manufacturing the transient voltage suppressor having a dopant or carrier concentration in a portion of a gate region near a Zener region that is different from a dopant concentration in a portion of a gate region that is away from the Zener region.
摘要翻译： 瞬态电压抑制器和制造瞬态电压抑制器的方法，该电压抑制器在齐纳一区域附近的栅极区域的与偏离齐纳一区域的栅极区域的一部分中的掺杂浓度不同的部分中具有掺杂剂或载流子浓度。
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公开(公告)号：US20090250720A1
公开(公告)日：2009-10-08
申请号：US12098369
申请日：2008-04-04
IPC分类号： H01L29/866 , H01L21/20
CPC分类号： H01L29/87 , H01L29/747 , H01L29/866
摘要： Transient voltage suppressor and method for manufacturing the transient voltage suppressor having a dopant or carrier concentration in a portion of a gate region near a Zener region that is different from a dopant concentration in a portion of a gate region that is away from the Zener region.
摘要翻译： 瞬态电压抑制器和制造瞬态电压抑制器的方法，该电压抑制器在齐纳一区域附近的栅极区域的与偏离齐纳一区域的栅极区域的一部分中的掺杂浓度不同的部分中具有掺杂剂或载流子浓度。
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公开(公告)号：US07339203B2
公开(公告)日：2008-03-04
申请号：US11317340
申请日：2005-12-22
IPC分类号： H01H29/32 , H01L21/332
CPC分类号： H01L29/747 , H01L29/0657 , H01L29/74
摘要： A thyristor and a method for manufacturing the thyristor that includes a gate region extending from the first major surface into a semiconductor substrate and an anode region extending from the second major surface into the semiconductor substrate. A cathode region extends into a portion of the gate region. Optionally, enhanced doped regions extend into the gate and anode regions. A mesa structure having a height HG is formed from the first major surface and a mesa structure having a height HA is formed from the second major surface. The gate region extends under the first major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HG. The anode region extends under the second major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HA.
摘要翻译： 晶闸管和制造晶闸管的方法，其包括从第一主表面延伸到半导体衬底的栅极区域和从第二主表面延伸到半导体衬底的阳极区域。 阴极区域延伸到栅极区域的一部分。 可选地，增强的掺杂区域延伸到栅极和阳极区域。 由第一主表面形成具有高度H SUB的台面结构，并且由第二主表面形成具有高度H A A的台面结构。 栅极区域延伸在半导体衬底的第一主表面之下，并且其垂直延伸到半导体衬底中，该距离大于高度H G。 阳极区域延伸在半导体衬底的第二主表面之下，并且其垂直延伸到半导体衬底中，该距离大于高度H A A。
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公开(公告)号：US20070145407A1
公开(公告)日：2007-06-28
申请号：US11317340
申请日：2005-12-22
IPC分类号： H01L29/74
CPC分类号： H01L29/747 , H01L29/0657 , H01L29/74
摘要： A thyristor and a method for manufacturing the thyristor that includes a gate region extending from the first major surface into a semiconductor substrate and an anode region extending from the second major surface into the semiconductor substrate. A cathode region extends into a portion of the gate region. Optionally, enhanced doped regions extend into the gate and anode regions. A mesa structure having a height HG is formed from the first major surface and a mesa structure having a height HA is formed from the second major surface. The gate region extends under the first major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HG. The anode region extends under the second major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HA.
摘要翻译： 晶闸管和制造晶闸管的方法，其包括从第一主表面延伸到半导体衬底的栅极区域和从第二主表面延伸到半导体衬底的阳极区域。 阴极区域延伸到栅极区域的一部分。 可选地，增强的掺杂区域延伸到栅极和阳极区域。 由第一主表面形成具有高度H SUB的台面结构，并且由第二主表面形成具有高度H A A的台面结构。 栅极区域延伸在半导体衬底的第一主表面之下，并且其垂直延伸到半导体衬底中，该距离大于高度H G。 阳极区域延伸在半导体衬底的第二主表面之下，并且其垂直延伸到半导体衬底中，该距离大于高度H A A。
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公开(公告)号：US07205583B1
公开(公告)日：2007-04-17
申请号：US11317213
申请日：2005-12-22
IPC分类号： H01L29/74 , H01L21/332
CPC分类号： H01L29/74 , H01L29/66363
摘要： A thyristor and a method for manufacturing the thyristor that includes providing a semiconductor substrate that has first and second major surfaces. A first doped region is formed in the semiconductor substrate, wherein the first doped extends from the first major surface into the semiconductor substrate. The first doped region has a vertical boundary that has a notched portion. A second doped region is formed in first doped region, wherein the second doped region extends from the first major surface into the first doped region. A third doped region is formed in the semiconductor substrate, wherein the third doped region extends from the second major surface into the semiconductor substrate.
摘要翻译： 一种晶闸管和一种制造晶闸管的方法，包括提供具有第一和第二主表面的半导体衬底。 第一掺杂区形成在半导体衬底中，其中第一掺杂从第一主表面延伸到半导体衬底中。 第一掺杂区域具有具有凹口部分的垂直边界。 在第一掺杂区域中形成第二掺杂区域，其中第二掺杂区域从第一主表面延伸到第一掺杂区域。 第三掺杂区域形成在半导体衬底中，其中第三掺杂区域从第二主表面延伸到半导体衬底中。
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