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    STAGE MITIGATION OF INTERCONNECT VARIABILITY
    3.
    发明申请
    STAGE MITIGATION OF INTERCONNECT VARIABILITY 有权
    互联不稳定性阶段缓解

    公开(公告)号：US20090019415A1

    公开(公告)日：2009-01-15

    申请号：US12237246

    申请日：2008-09-24

    申请人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

    发明人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.

    摘要翻译： 本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。 在本发明的技术下，确定了芯片互连的全局和详细路由。 此后，执行虚拟填充估计和网格基金属密度估计。 然后，基于CMP模型，获得金属厚度的可变图。 基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。 然后将这些接线网重新布线以优化芯片。

    Design stage mitigation of interconnect variability
    4.
    发明授权
    Design stage mitigation of interconnect variability 有权
    设计阶段缓解互连变异性

    公开(公告)号：US07448014B2

    公开(公告)日：2008-11-04

    申请号：US11370538

    申请日：2006-03-08

    申请人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

    发明人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.

    摘要翻译： 本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。 在本发明的技术下，确定了芯片互连的全局和详细路由。 此后，执行虚拟填充估计和网格基金属密度估计。 然后，基于CMP模型，获得金属厚度的可变图。 基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。 然后将这些接线网重新布线以优化芯片。

    Stage mitigation of interconnect variability
    5.
    发明授权
    Stage mitigation of interconnect variability 有权
    阶段缓解互连变异性

    公开(公告)号：US07930669B2

    公开(公告)日：2011-04-19

    申请号：US12237246

    申请日：2008-09-24

    申请人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

    发明人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.

    摘要翻译： 本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。 在本发明的技术下，确定了芯片互连的全局和详细路由。 此后，执行虚拟填充估计和网格基金属密度估计。 然后，基于CMP模型，获得金属厚度的可变图。 基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。 然后将这些接线网重新布线以优化芯片。

    System and method for global circuit routing incorporating estimation of critical area estimate metrics
    6.
    发明授权
    System and method for global circuit routing incorporating estimation of critical area estimate metrics 失效
    用于全局电路路由的系统和方法，其中包括关键面积估计度量的估计

    公开(公告)号：US07685553B2

    公开(公告)日：2010-03-23

    申请号：US11733795

    申请日：2007-04-11

    申请人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

    发明人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.

    摘要翻译： 电子电路布局细化方法和系统。 在电路布局区域上定义了一个大小相同的瓷砖网格。 电网的每个瓦片具有与放置在电路布局区域上的电路的关键面积估计相关联的相应临界面积估计量度。 执行用于放置在电网的多个瓦片内的电路的全局电路布线。 在对电路执行详细的电路布线之前执行分配给电网的各个瓦片的关键面积估计度量的估计。 在估计关键区域估计度量之后，调整全局电路路由，以便改进分配给网格的至少一个瓦片的相应临界区域估计度量。 然后生成经调整的全局电路布线。

    SYSTEM AND METHOD FOR GLOBAL CIRCUIT ROUTING INCORPORATING ESTIMATION OF CRITICAL AREA ESTIMATE METRICS
    7.
    发明申请
    SYSTEM AND METHOD FOR GLOBAL CIRCUIT ROUTING INCORPORATING ESTIMATION OF CRITICAL AREA ESTIMATE METRICS 失效
    全球电路路由系统与方法，适用于关键领域估算的估计

    公开(公告)号：US20080256502A1

    公开(公告)日：2008-10-16

    申请号：US11733795

    申请日：2007-04-11

    申请人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

    发明人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.

    摘要翻译： 电子电路布局细化方法和系统。 在电路布局区域上定义了一个大小相同的瓷砖网格。 电网的每个瓦片具有与放置在电路布局区域上的电路的关键面积估计相关联的相应临界面积估计量度。 执行用于放置在电网的多个瓦片内的电路的全局电路布线。 在对电路执行详细的电路布线之前执行分配给电网的各个瓦片的关键面积估计度量的估计。 在估计关键区域估计度量之后，调整全局电路路由，以便改进分配给网格的至少一个瓦片的相应临界区域估计度量。 然后生成经调整的全局电路布线。

    TECHNIQUES FOR FAST AREA-EFFICIENT INCREMENTAL PHYSICAL SYNTHESIS
    8.
    发明申请
    TECHNIQUES FOR FAST AREA-EFFICIENT INCREMENTAL PHYSICAL SYNTHESIS 审中-公开
    用于快速增强体力合成的技术

    公开(公告)号：US20100257499A1

    公开(公告)日：2010-10-07

    申请号：US12416960

    申请日：2009-04-02

    申请人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Ying Zhou

    发明人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Ying Zhou

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A fast technique for circuit optimization in a physical synthesis flow iteratively repeats slew-driven (timerless) buffering and repowering with a changing slew target. Buffers are added as necessary with each iteration to bring the nets in line with the new slew target, but any nets having positive slack from the previous iteration are skipped, and that slack information is cached for future timing analysis. Buffer insertion is iteratively repeated with incrementally decreasing slew until a minimum slew is reached, or when none of the nets have negative slack. Iteratively repeating the timerless buffering and repowering while gradually decreasing the slew constraint in this manner results in a design structure which retains high quality of results with significantly smaller area and wire length, and with only a small computational overhead.

    摘要翻译： 物理合成流中电路优化的快速技术可以迭代地重复使用转换驱动（定时器）缓冲并使用更改的转换目标重新启动。 根据需要，每次迭代添加缓冲区，使网格与新的转换目标一致，但是跳过与上一次迭代相反的任何网络，并且缓存信息被缓存以便将来进行时序分析。 缓冲区插入被迭代重复，逐渐减小，直到达到最小的转差，或者当没有网络有负的松弛时。 以这种方式迭代地重复定时器缓冲和重新赋能，同时以这种方式逐渐减小摆动约束导致设计结构，其保持高质量的结果，具有明显更小的面积和导线长度，并且仅具有小的计算开销。

    Design Routability Using Multiplexer Structures
    9.
    发明申请
    Design Routability Using Multiplexer Structures 失效
    使用多路复用器结构设计路由

    公开(公告)号：US20130086537A1

    公开(公告)日：2013-04-04

    申请号：US13248119

    申请日：2011-09-29

    申请人： Charles J. Alpert ,  Victor N. Kravets ,  Zhuo Li ,  Louise H. Trevillyan ,  Ying Zhou

    发明人： Charles J. Alpert ,  Victor N. Kravets ,  Zhuo Li ,  Louise H. Trevillyan ,  Ying Zhou

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Mechanisms are provided for generating a logic design of an integrated circuit device. An initial logic design representation of the integrated circuit device is received and one or more areas of the initial logic design representation are identified where logic elements in the one or more areas can be replaced with one or more multiplexer tree structures. Logic elements in the one or more areas of the initial logic design representation are replaced with multiplexer tree structures to generate a modified logic design representation. The modified logic design representation is output to a physical synthesis system to generate a physical layout of the integrated circuit device based on the modified logic design representation.

    摘要翻译： 提供用于产生集成电路器件的逻辑设计的机构。 接收集成电路设备的初始逻辑设计表示，并且识别初始逻辑设计表示的一个或多个区域，其中一个或多个区域中的逻辑元件可被一个或多个多路复用器树结构替代。 初始逻辑设计表示的一个或多个区域中的逻辑元件被多路复用器树结构替代以生成修改的逻辑设计表示。 经修改的逻辑设计表示被输出到物理合成系统，以基于经修改的逻辑设计表示来生成集成电路器件的物理布局。

    Routability using multiplexer structures
    10.
    发明授权
    Routability using multiplexer structures 失效
    使用多路复用器结构的路由性

    公开(公告)号：US08539400B2

    公开(公告)日：2013-09-17

    申请号：US13248119

    申请日：2011-09-29

    申请人： Charles J. Alpert ,  Victor N. Kravets ,  Zhuo Li ,  Louise H. Trevillyan ,  Ying Zhou

    发明人： Charles J. Alpert ,  Victor N. Kravets ,  Zhuo Li ,  Louise H. Trevillyan ,  Ying Zhou

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Mechanisms are provided for generating a logic design of an integrated circuit device. An initial logic design representation of the integrated circuit device is received and one or more areas of the initial logic design representation are identified where logic elements in the one or more areas can be replaced with one or more multiplexer tree structures. Logic elements in the one or more areas of the initial logic design representation are replaced with multiplexer tree structures to generate a modified logic design representation. The modified logic design representation is output to a physical synthesis system to generate a physical layout of the integrated circuit device based on the modified logic design representation.

    摘要翻译： 提供用于产生集成电路器件的逻辑设计的机构。 接收集成电路设备的初始逻辑设计表示，并且识别初始逻辑设计表示的一个或多个区域，其中一个或多个区域中的逻辑元件可被一个或多个多路复用器树结构替代。 初始逻辑设计表示的一个或多个区域中的逻辑元件被多路复用器树结构替代以生成修改的逻辑设计表示。 经修改的逻辑设计表示被输出到物理合成系统，以基于经修改的逻辑设计表示来生成集成电路器件的物理布局。