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    System and method for global circuit routing incorporating estimation of critical area estimate metrics
    1.
    发明授权
    System and method for global circuit routing incorporating estimation of critical area estimate metrics 失效
    用于全局电路路由的系统和方法，其中包括关键面积估计度量的估计

    公开(公告)号：US07685553B2

    公开(公告)日：2010-03-23

    申请号：US11733795

    申请日：2007-04-11

    申请人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

    发明人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.

    摘要翻译： 电子电路布局细化方法和系统。 在电路布局区域上定义了一个大小相同的瓷砖网格。 电网的每个瓦片具有与放置在电路布局区域上的电路的关键面积估计相关联的相应临界面积估计量度。 执行用于放置在电网的多个瓦片内的电路的全局电路布线。 在对电路执行详细的电路布线之前执行分配给电网的各个瓦片的关键面积估计度量的估计。 在估计关键区域估计度量之后，调整全局电路路由，以便改进分配给网格的至少一个瓦片的相应临界区域估计度量。 然后生成经调整的全局电路布线。

    Method and apparatus for net-aware critical area extraction
    3.
    发明授权
    Method and apparatus for net-aware critical area extraction 失效
    网络关键区域提取的方法和装置

    公开(公告)号：US07661080B2

    公开(公告)日：2010-02-09

    申请号：US11626576

    申请日：2007-01-24

    申请人： Evanthia Papadopoulou ,  Sarah Braasch ,  Mervyn Y. Tan

    发明人： Evanthia Papadopoulou ,  Sarah Braasch ,  Mervyn Y. Tan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, where the net is made up of a plurality of interconnected shapes spanning one or more layers of the integrated circuit. All generators for opens are then defined and identified. The Voronoi diagram of the identified generators is computed, and the critical area is computed in accordance with the Voronoi diagram.

    摘要翻译： 在一个实施例中，本发明是一种用于网络感知关键区域提取的方法和装置。 用于确定集成电路的关键区域的本发明方法的一个实施例包括将对应于集成电路的网络建模为图，其中网络由跨越集成电路的一个或多个层的多个互连形状组成。 然后定义和识别所有用于打开的发生器。 计算识别的发电机的Voronoi图，并根据Voronoi图计算临界面积。

    IC layout optimization to improve yield
    4.
    发明授权
    IC layout optimization to improve yield 失效
    IC布局优化提高产量

    公开(公告)号：US07503020B2

    公开(公告)日：2009-03-10

    申请号：US11424922

    申请日：2006-06-19

    申请人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

    发明人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

    摘要翻译： 一种用于优化集成电路设计以提高制造产量的方法和服务。 本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。 本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

    SYSTEM AND METHOD FOR GLOBAL CIRCUIT ROUTING INCORPORATING ESTIMATION OF CRITICAL AREA ESTIMATE METRICS
    5.
    发明申请
    SYSTEM AND METHOD FOR GLOBAL CIRCUIT ROUTING INCORPORATING ESTIMATION OF CRITICAL AREA ESTIMATE METRICS 失效
    全球电路路由系统与方法，适用于关键领域估算的估计

    公开(公告)号：US20080256502A1

    公开(公告)日：2008-10-16

    申请号：US11733795

    申请日：2007-04-11

    申请人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

    发明人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.

    摘要翻译： 电子电路布局细化方法和系统。 在电路布局区域上定义了一个大小相同的瓷砖网格。 电网的每个瓦片具有与放置在电路布局区域上的电路的关键面积估计相关联的相应临界面积估计量度。 执行用于放置在电网的多个瓦片内的电路的全局电路布线。 在对电路执行详细的电路布线之前执行分配给电网的各个瓦片的关键面积估计度量的估计。 在估计关键区域估计度量之后，调整全局电路路由，以便改进分配给网格的至少一个瓦片的相应临界区域估计度量。 然后生成经调整的全局电路布线。

    METHOD AND APPARATUS FOR NET-AWARE CRITICAL AREA EXTRACTION
    6.
    发明申请
    METHOD AND APPARATUS FOR NET-AWARE CRITICAL AREA EXTRACTION 失效
    网络关键领域提取的方法和装置

    公开(公告)号：US20080178137A1

    公开(公告)日：2008-07-24

    申请号：US11626576

    申请日：2007-01-24

    申请人： Evanthia Papadopoulou ,  Sarah Braasch ,  Mervyn Y. Tan

    发明人： Evanthia Papadopoulou ,  Sarah Braasch ,  Mervyn Y. Tan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： In one embodiment, the present invention is a method and apparatus for net-aware critical area extraction. One embodiment of the inventive method for determining the critical area of an integrated circuit includes modeling a net corresponding to the integrated circuit as a graph, where the net is made up of a plurality of interconnected shapes spanning one or more layers of the integrated circuit. All generators for opens are then defined and identified. The Voronoi diagram of the identified generators is computed, and the critical area is computed in accordance with the Voronoi diagram.

    摘要翻译： 在一个实施例中，本发明是一种用于网络感知关键区域提取的方法和装置。 用于确定集成电路的关键区域的本发明方法的一个实施例包括将对应于集成电路的网络建模为图，其中网络由跨越集成电路的一个或多个层的多个互连形状组成。 然后定义和识别所有用于打开的发生器。 计算识别的发电机的Voronoi图，并根据Voronoi图计算临界面积。

    IC Layout Optimization To Improve Yield
    7.
    发明申请
    IC Layout Optimization To Improve Yield 失效
    IC布局优化提高产量

    公开(公告)号：US20070294648A1

    公开(公告)日：2007-12-20

    申请号：US11424922

    申请日：2006-06-19

    申请人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

    发明人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

    摘要翻译： 一种用于优化集成电路设计以提高制造产量的方法和服务。 本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。 本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

    Sample probability of fault function determination using critical defect size map
    8.
    发明授权
    Sample probability of fault function determination using critical defect size map 失效
    使用关键缺陷尺寸图的故障函数确定的样本概率

    公开(公告)号：US07310788B2

    公开(公告)日：2007-12-18

    申请号：US10906549

    申请日：2005-02-24

    申请人： Robert J. Allen ,  Mervyn Y. Tan

    发明人： Robert J. Allen ,  Mervyn Y. Tan

    IPC分类号： G06F17/50 ,  G06F17/10

    CPC分类号： G06F17/504

    摘要： Methods, systems and program products for determining a probability of fault (POF) function using critical defect size maps. Methods for an exact or a sample POF function are provided. Critical area determinations can also be supplied based on the exact or sample POF functions. The invention provides a less computationally complex and storage-intensive methodology.

    摘要翻译： 使用关键缺陷尺寸图确定故障概率（POF）功能的方法，系统和程序产品。 提供精确或样本POF功能的方法。 也可以根据POF功能的准确或取样来提供关键区域测定。 本发明提供了较少的计算复杂性和存储密集型方法。

    IC layout optimization to improve yield
    10.
    发明授权
    IC layout optimization to improve yield 有权
    IC布局优化提高产量

    公开(公告)号：US07818694B2

    公开(公告)日：2010-10-19

    申请号：US12342353

    申请日：2008-12-23

    申请人： Robert J Allen ,  Faye D Baker ,  Albert M Chu ,  Michael S Gray ,  Jason Hibbeler ,  Daniel N Maynard ,  Mervyn Y Tan ,  Robert F Walker

    发明人： Robert J Allen ,  Faye D Baker ,  Albert M Chu ,  Michael S Gray ,  Jason Hibbeler ,  Daniel N Maynard ,  Mervyn Y Tan ,  Robert F Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

    摘要翻译： 使用制造数据和算法优化集成电路设计以提高制造产量，以识别故障概率高的区域，即关键区域。 该过程进一步改变电路设计的布局以减少临界面积，从而降低制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。