公开(公告)号：US20130263068A1

公开(公告)日：2013-10-03

申请号：US13431368

申请日：2012-03-27

申请人： Minsik Cho ,  Ruchir Puri ,  Haoxing Ren ,  Xiaoping Tang ,  Hua Xiang ,  Matthew Mantell Ziegler

发明人： Minsik Cho ,  Ruchir Puri ,  Haoxing Ren ,  Xiaoping Tang ,  Hua Xiang ,  Matthew Mantell Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/06

摘要： Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein.

摘要翻译： 本文提供了相对排序电路合成的系统和方法。 一个方面提供了通过计算设备可访问的至少一个处理器生成至少一个电路设计; 其中产生至少一个电路设计包括：基于至少一个电路设计布局生成至少一个相对顺序结构，所述至少一个相对顺序结构包括与至少一个电路元件相关联的至少一个放置约束; 根据所述至少一个放置约束将与所述至少一个放置约束相关联的所述至少一个电路元件放置在电路设计内; 以及将不与所述至少一个放置约束相关联的电路元件放置在所述电路设计内。 本文还描述了其它实施例和方面。

公开(公告)号：US08756541B2

公开(公告)日：2014-06-17

申请号：US13431368

申请日：2012-03-27

申请人： Minsik Cho ,  Ruchir Puri ,  Haoxing Ren ,  Xiaoping Tang ,  Hua Xiang ,  Matthew Mantell Ziegler

发明人： Minsik Cho ,  Ruchir Puri ,  Haoxing Ren ,  Xiaoping Tang ,  Hua Xiang ,  Matthew Mantell Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/06

摘要： Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein.

摘要翻译： 本文提供了相对排序电路合成的系统和方法。 一个方面提供了通过计算设备可访问的至少一个处理器生成至少一个电路设计; 其中产生至少一个电路设计包括：基于至少一个电路设计布局生成至少一个相对顺序结构，所述至少一个相对顺序结构包括与至少一个电路元件相关联的至少一个放置约束; 根据所述至少一个放置约束将与所述至少一个放置约束相关联的所述至少一个电路元件放置在电路设计内; 以及将不与所述至少一个放置约束相关联的电路元件放置在所述电路设计内。 本文还描述了其它实施例和方面。

公开(公告)号：US20120196230A1

公开(公告)日：2012-08-02

申请号：US13016033

申请日：2011-01-28

申请人： Minsik Cho ,  Xiaoping Tang

发明人： Minsik Cho ,  Xiaoping Tang

IPC分类号： G03F7/20 ,  G03B27/00 ,  G06F17/50

CPC分类号： G03F1/70 ,  G03F7/70433 ,  G03F7/70475

摘要： An initial layout of at least a portion of a given layer of an integrated circuit design is decomposed into multiple sub-layouts by splitting each of a plurality of shapes of the initial layout into multiple segments, constructing a constraint graph to represent relationships between the segments, reducing the constraint graph to a stitch graph, determining at least one cut line of the stitch graph, and generating a decomposed layout based on the determined cut line. The decomposed layout in an illustrative embodiment includes first and second sub-layouts comprising respective disjoint subsets of the segments, with each of the sub-layouts of the decomposed layout being associated with a different pattern mask of a double patterning lithography process. The layout decomposition process advantageously minimizes the number of stitches between the sub-layouts without introducing excessive computational complexity.

摘要翻译： 将集成电路设计的给定层的至少一部分的初始布局通过将初始布局的多个形状中的每一个划分成多个段来分解成多个子布局，构建约束图以表示段之间的关系 将所述约束图减少到针迹图，确定所述针迹图的至少一个切割线，以及基于所确定的切割线来生成分解的布局。 在说明性实施例中的分解布局包括包括段的相应不相交子集的第一和第二子布局，其中分解布局的每个子布局与双图案化光刻工艺的不同图案掩模相关联。 布局分解过程有利地使子布局之间的线迹数目最小化，而不引入过多的计算复杂度。

公开(公告)号：US08799844B2

公开(公告)日：2014-08-05

申请号：US13016033

申请日：2011-01-28

申请人： Minsik Cho ,  Xiaoping Tang

发明人： Minsik Cho ,  Xiaoping Tang

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  G03F7/70433 ,  G03F7/70475

摘要： An initial layout of at least a portion of a given layer of an integrated circuit design is decomposed into multiple sub-layouts by splitting each of a plurality of shapes of the initial layout into multiple segments, constructing a constraint graph to represent relationships between the segments, reducing the constraint graph to a stitch graph, determining at least one cut line of the stitch graph, and generating a decomposed layout based on the determined cut line. The decomposed layout in an illustrative embodiment includes first and second sub-layouts comprising respective disjoint subsets of the segments, with each of the sub-layouts of the decomposed layout being associated with a different pattern mask of a double patterning lithography process. The layout decomposition process advantageously minimizes the number of stitches between the sub-layouts without introducing excessive computational complexity.

摘要翻译： 将集成电路设计的给定层的至少一部分的初始布局通过将初始布局的多个形状中的每一个划分成多个段来分解成多个子布局，构建约束图以表示段之间的关系 将所述约束图减少到针迹图，确定所述针迹图的至少一个切割线，以及基于所确定的切割线来生成分解的布局。 在说明性实施例中的分解布局包括包括段的相应不相交子集的第一和第二子布局，其中分解布局的每个子布局与双图案化光刻工艺的不同图案掩模相关联。 布局分解过程有利地使子布局之间的线迹数目最小化，而不引入过多的计算复杂度。

公开(公告)号：US08566761B2

公开(公告)日：2013-10-22

申请号：US13301107

申请日：2011-11-21

申请人： Hua Xiang ,  Minsik Cho ,  Haoxing Ren ,  Matthew M Ziegler ,  Ruchir Puri

发明人： Hua Xiang ,  Minsik Cho ,  Haoxing Ren ,  Matthew M Ziegler ,  Ruchir Puri

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/504

摘要： The present disclosure relates to a computer-based method and apparatus for determining datapath bit slices. A first two-way search is performed between an input vector and an output vector to identify gates in a datapath. A network flow is then constructed including the gates identified, and a min-cost max-flow algorithm is applied to the network flow to derive matching bit pairs between the input vector and the output vector. Next, the datapath bit slices are determined by performing a second two-way search between each of a starting bit in the input vector and an ending bit in the output vector of each of the matching bit pairs.

摘要翻译： 本公开涉及一种用于确定数据路径位片的基于计算机的方法和装置。 在输入向量和输出向量之间执行第一个双向搜索以识别数据通路中的门。 然后构建包括所识别的门的网络流，并且将最小成本最大流算法应用于网络流以导出输入向量和输出向量之间的匹配比特对。 接下来，通过在输入向量中的起始位和每个匹配位对的输出向量中的结束位之间执行第二双向搜索来确定数据通路位片。

公开(公告)号：US08516412B2

公开(公告)日：2013-08-20

申请号：US13222928

申请日：2011-08-31

申请人： Minsik Cho ,  Alvan W. Ng ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Matthew M. Ziegler

发明人： Minsik Cho ,  Alvan W. Ng ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Matthew M. Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/505

摘要： In one embodiment, the invention is a method and apparatus for soft hierarchy-based synthesis for large-scale, high-performance circuits. One embodiment of a method for physically synthesizing a design of an integrated circuit includes compiling a logical description of the design into a flattened netlist, extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy.

摘要翻译： 在一个实施例中，本发明是用于大规模，高性能电路的基于层次的软合成的方法和装置。 用于物理地合成集成电路的设计的方法的一个实施例包括将设计的逻辑描述编译成扁平网表，从扁平化网表中提取软层次，其中软层次结构定义了裸片上的边界， 集成电路被允许移动，并且根据软层次将集成电路的单元放置在管芯上。

公开(公告)号：US20120054699A1

公开(公告)日：2012-03-01

申请号：US12868086

申请日：2010-08-25

申请人： Minsik Cho ,  Victor N. Kravets ,  Smita Krishnaswamy ,  Dorothy Kucar ,  Jagannathan Narasimhan ,  Ruchir Puri ,  Haifeng Qian ,  Haoxing Ren ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Hua Xiang ,  Matthew M. Ziegler

发明人： Minsik Cho ,  Victor N. Kravets ,  Smita Krishnaswamy ,  Dorothy Kucar ,  Jagannathan Narasimhan ,  Ruchir Puri ,  Haifeng Qian ,  Haoxing Ren ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Hua Xiang ,  Matthew M. Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.

摘要翻译： 示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成， 对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

公开(公告)号：US08495552B1

公开(公告)日：2013-07-23

申请号：US13536601

申请日：2012-06-28

申请人： Minsik Cho ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Matthew M. Ziegler

发明人： Minsik Cho ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Matthew M. Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/84

摘要： Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined criteria. Local-clock-buffers are also preplaced together with the latches further improving datapath performance.

摘要翻译： 在集成电路物理合成期间，锁存器和本地时钟缓冲器将自动放置。 在物理布置数据通路之前，基于数据通路的逻辑表示和引脚的固定放置位置为锁存器分配位置。 所计算的锁存位置根据某些预定标准优化数据通路。 本地时钟缓冲器也被预置在一起，锁存器进一步提高了数据通路性能。

公开(公告)号：US20090031275A1

公开(公告)日：2009-01-29

申请号：US11781692

申请日：2007-07-23

申请人： Minsik Cho ,  Zhigang Pan

发明人： Minsik Cho ,  Zhigang Pan

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method for performing global routing on an integrated circuit design is disclosed. The integrated circuit design is initially divided into multiple G-cells. The G-cells are interconnected by a set of nets. The set of nets is then decomposed into corresponding wires. The wires are prerouted to interconnect the G-cells. BoxRouting is performed on the wires until all the wires are routed. Finally, postrouting is performed on the wires.

摘要翻译： 公开了一种在集成电路设计上执行全局路由的方法。 集成电路设计最初分为多个G单元。 G单元通过一组网络互连。 然后将该组网络分解为相应的线。 电线被预先引导以连接G电池。 在线路上执行BoxRouting，直到所有的电线都被路由。 最后，在导线上执行后路径。

公开(公告)号：US20130326451A1

公开(公告)日：2013-12-05

申请号：US13487062

申请日：2012-06-01

申请人： Minsik Cho ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Matthew M. Ziegler

发明人： Minsik Cho ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Matthew M. Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/84

摘要： Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined criteria. Local-clock-buffers are also preplaced together with the latches further improving datapath performance.

摘要翻译： 在集成电路物理合成期间，锁存器和本地时钟缓冲器将自动放置。 在物理布置数据通路之前，基于数据通路的逻辑表示和引脚的固定放置位置为锁存器分配位置。 所计算的锁存位置根据某些预定标准优化数据通路。 本地时钟缓冲器也被预置在一起，锁存器进一步提高了数据通路性能。