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1.发明授权Directory based cache coherency system supporting multiple instruction processor and input/output caches 有权基于目录的高速缓存一致性系统支持多指令处理器和输入/输出缓存公开(公告)号：US06438659B1
公开(公告)日：2002-08-20
申请号：US09645233
申请日：2000-08-24
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0886 , G06F2212/621
摘要： A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/0) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.
摘要翻译： 公开了一种基于目录的高速缓存一致性系统，用于具有通过共享主存储器耦合的多个指令处理器（IP）和多个输入/输出（I / O）单元的数据处理系统。 该系统包括一个或多个IP高速缓冲存储器，每个IP缓存存储器分别耦合到一个或多个IP和共享主存储器，用于高速缓存被称为高速缓存线的数据单元。 该系统还包括一个或多个I / O单元内的I / O存储器，每个I / O存储器耦合到共享主存储器，用于存储从共享主存储器检索的高速缓存线。 通过使用存储系统中每个缓存行的状态的中央目录来维护一致性。 该状态表示IP高速缓存和具有给定高速缓存行的有效副本的I / O存储器的身份，并进一步标识与高速缓存行相关联的一组访问权限，即高速缓存行“状态”。 高速缓存行状态用于实现跟踪高速缓存行的状态机，并且仅确保在存储器系统内维护的有效副本。 根据系统的另一方面，主存储器对驻留在IP高速缓存中的所有高速缓存行执行连续跟踪和控制功能。 相比之下，系统仅为提供给I / O单元的预定高速缓存行维护跟踪和控制功能，从而可以减少系统开销。 一致性系统还支持在不同大小的高速缓存线上运行的多个异构指令处理器。
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2.发明授权Directory-based cache coherency system supporting multiple instruction processor and input/output caches 失效基于目录的高速缓存一致性系统支持多指令处理器和输入/输出缓存公开(公告)号：US06587931B1
公开(公告)日：2003-07-01
申请号：US09001598
申请日：1997-12-31
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0886 , G06F2212/621
摘要： A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.
摘要翻译： 公开了一种基于目录的高速缓存一致性系统，用于具有通过共享主存储器耦合的多个指令处理器（IP）和多个输入/输出（I / O）单元的数据处理系统。 该系统包括一个或多个IP高速缓冲存储器，每个IP缓存存储器分别耦合到一个或多个IP和共享主存储器，用于高速缓存被称为高速缓存线的数据单元。 该系统还包括一个或多个I / O单元内的I / O存储器，每个I / O存储器耦合到共享主存储器，用于存储从共享主存储器检索的高速缓存线。 通过使用存储系统中每个缓存行的状态的中央目录来维护一致性。 该状态表示IP高速缓存和具有给定高速缓存行的有效副本的I / O存储器的身份，并进一步标识与高速缓存行相关联的一组访问权限，即高速缓存行“状态”。 高速缓存行状态用于实现跟踪高速缓存行的状态机，并且仅确保在存储器系统内维护的有效副本。 根据系统的另一方面，主存储器对驻留在IP高速缓存中的所有高速缓存行执行连续跟踪和控制功能。 相比之下，系统仅为提供给I / O单元的预定高速缓存行维护跟踪和控制功能，从而可以减少系统开销。 一致性系统还支持在不同大小的高速缓存线上运行的多个异构指令处理器。
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3.发明授权High-speed memory storage unit for a multiprocessor system having integrated directory and data storage subsystems 失效具有集成目录和数据存储子系统的多处理器系统的高速存储器存储单元公开(公告)号：US06415364B1
公开(公告)日：2002-07-02
申请号：US09001588
申请日：1997-12-31
申请人： Mitchell A. Bauman , Eugene A. Rodi
发明人： Mitchell A. Bauman , Eugene A. Rodi
IPC分类号： G06F1206
CPC分类号： G06F12/0817
摘要： A high-speed memory system is disclosed for use in supporting a directory-based cache coherency protocol. The memory system includes at least one data system for storing data, and a corresponding directory system for storing the corresponding cache coherency information. Each data storage operation involves a block transfer operation performed to multiple sequential addresses within the data system. Each data storage operation occurs in conjunction with an associated read-modify-write operation performed on cache coherency information stored within the corresponding directory system. Multiple ones of the data storage operations may be occurring within one or more of the data systems in parallel. Likewise, multiple ones of the read-modify-write operations may be performed to one or more of the directory systems in parallel. The transfer of address, control, and data signals for these concurrently performed operations occurs in an interleaved manner. The use of block transfer operations in combination with the interleaved transfer of signals to memory systems prevents the overhead associated with the read-modify-write operations from substantially impacting system performance. This is true even when data and directory systems are implemented using the same memory technology.
摘要翻译： 公开了一种用于支持基于目录的高速缓存一致性协议的高速存储器系统。 存储器系统包括用于存储数据的至少一个数据系统和用于存储对应的高速缓存一致性信息的相应目录系统。 每个数据存储操作涉及对数据系统内的多个连续地址执行的块传送操作。 每个数据存储操作结合对相应目录系统中存储的高速缓存一致性信息执行的关联读 - 修改 - 写操作进行。 多个数据存储操作可以并行地在一个或多个数据系统内进行。 同样地，并行地对一个或多个目录系统执行多个读 - 修改 - 写操作。 这些并发执行的操作的地址，控制和数据信号的传送以交错的方式发生。 使用块传送操作与对存储器系统的信号的交错传送相结合，防止与读取 - 修改 - 写入操作相关联的开销基本上影响系统性能。 即使使用相同的内存技术来实现数据和目录系统，这一点也是如此。
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4.发明授权System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory module 有权用于执行共享存储器模块中的多个存储体和接口的并行初始化和测试的系统和方法公开(公告)号：US06381715B1
公开(公告)日：2002-04-30
申请号：US09223850
申请日：1998-12-31
IPC分类号： G11C2900
摘要： A system and method for testing and initializing a memory including multiple memory banks or a memory module partitioned into logical memory units. A plurality of memory exerciser testers are provided, one for each of the plurality of memory banks. Each of the memory exerciser testers includes an address generator to generate a sequence of memory bank addresses to successively address each of the memory banks in a cyclic manner, while each of the address generators concurrently addresses a different one of the memory banks. A data pattern generator is coupled to a corresponding one of the address generators to receive a data pattern control signal upon each output of each of the memory bank addresses generated by its corresponding address generator. The data pattern generator outputs a unique data pattern to the memory bank identified by the memory bank address in response to each occurrence of the data pattern control signal. A plurality of address initialization registers are provided, one for each of the plurality of exerciser testers. Each of the address initialization registers stores an initial memory bank address for one of the memory banks such that each of the address generators is preset to initially address a different one of the memory banks. In this manner, each memory bank is addressed by a different one of the address generators at any given time, which provides for concurrent testing of all memory banks and memory interfaces.
摘要翻译： 一种用于测试和初始化存储器的系统和方法，所述存储器包括多个存储体或分为逻辑存储单元的存储器模块。 提供了多个存储器练习器测试器，一个用于多个存储体中的每一个。 每个存储器练习器测试器包括地址发生器，以产生一系列存储体地址，以循环方式连续寻址每个存储体，同时每个地址生成器同时寻址不同的存储体。 数据模式发生器耦合到对应的一个地址发生器，以在由其对应的地址发生器产生的每个存储体地址的每个输出上接收数据模式控制信号。 响应于数据模式控制信号的每次出现，数据模式发生器将唯一的数据模式输出到由存储体地址识别的存储体。 提供了多个地址初始化寄存器，其中一个用于多个锻炼测试器中的每一个。 每个地址初始化寄存器存储用于存储器组之一的初始存储体地址，使得每个地址生成器被预设为最初寻址不同的存储体。 以这种方式，每个存储体在任何给定时间由不同的地址生成器寻址，这提供了对所有存储体和存储器接口的并行测试。
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公开(公告)号：US07634709B2
公开(公告)日：2009-12-15
申请号：US09972490
申请日：2001-10-05
申请人： Mitchell A. Bauman , Eugene A. Rodi
发明人： Mitchell A. Bauman , Eugene A. Rodi
CPC分类号： G06F11/1044
摘要： Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. It uses ×4 bit DRAM devices organized in a code word of 128 data bit words and 16 check bits. These 16 check bits are generated in such a way as to provide a code capable of 4 bit adjacent error correction within a family (i.e., in a ×4 DRAM) and double bit non-adjacent error detection across the entire 128 bit word, with single bit correction across the word as well. Each device can be thought of as a separate family of bits, errors occurring in more than one family are not correctable, but may be detected if only one bit in each of two families is in error. Syndrome generation and regeneration are used together with a specific large code word. Decoding the syndrome and checking it against the regenerated syndrome yield data sufficient for providing the features described.
摘要翻译： 与DRAM芯片故障相关的错误校正和错误检测，特别是适配的服务器内存子系统。 它使用组织在128个数据位字和16个校验位的代码字中的x4位DRAM器件。 这16个校验位的生成方式是提供一个能够在一个系列内进行4位相邻纠错的代码（即，在x4 DRAM中）和跨整个128位字的双位非相邻错误检测的代码，其中单个 同时也纠正了这个词。 每个设备都可以被认为是一个独立的位系列，发生在多个系列中的错误是不可校正的，但是如果两个系列中的每一个中只有一位是错误的，则可能被检测到。 综合征生成和再生与特定的大码字一起使用。 对该综合征进行解码并针对再生综合征进行检查，产生足以提供所述特征的数据。
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6.发明授权公开(公告)号：US07167955B1
公开(公告)日：2007-01-23
申请号：US10745372
申请日：2003-12-23
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F11/1008 , G06F2212/1032
摘要： A system and method for testing and/or initializing a Directory Store in a directory-based coherent memory. In one illustrative embodiment, the directory-based coherent memory includes a Main Store for storing a number of data entries, a Directory Store for storing the directory state for at least some of the data entries in the Main Store, and a next state block for determining a next directory state for a requested data entry in response to a memory request. To provide access to the Directory Store, and in one illustrative embodiment, a selector is provided for selecting either the next directory state value provided by the next state block or another predetermined value. The other predetermined value may be, for example, a fixed data pattern, a variable data pattern, a specified value, or any other value suitable for initializing and/or testing the Directory Store. The output of the selector may be written to the Directory Store.
摘要翻译： 用于在基于目录的连贯内存中测试和/或初始化目录存储的系统和方法。 在一个说明性实施例中，基于目录的相干存储器包括用于存储多个数据条目的主存储器，用于存储主存储器中的至少一些数据条目的目录状态的目录存储器，以及下一个状态块 响应于存储器请求确定所请求的数据条目的下一目录状态。 为了提供对目录存储的访问，并且在一个说明性实施例中，提供了选择器，用于选择由下一个状态块提供的下一个目录状态值或另一个预定值。 另一个预定值可以是例如固定数据模式，可变数据模式，指定值或适用于初始化和/或测试目录库的任何其他值。 选择器的输出可能会写入目录存储。
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公开(公告)号：US07506110B2
公开(公告)日：2009-03-17
申请号：US11602689
申请日：2006-11-21
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G11C5/04
摘要： In general, techniques are described for initializing a memory module in accordance with a programmable initialization sequence. A memory controller, for example, includes a programmable computer-readable medium that stores configuration data to control initialization of one or more memory modules. The memory controller includes an initialization control unit that outputs a sequence of commands to initialize the memory modules in accordance with the configuration data. The initialization control unit may select the sequence of commands from a set of predefined initialization sequences based on the configuration data.
摘要翻译： 通常，描述了根据可编程初始化序列来初始化存储器模块的技术。 存储器控制器例如包括存储配置数据以控制一个或多个存储器模块的初始化的可编程计算机可读介质。 存储器控制器包括：初始化控制单元，其根据配置数据输出用于初始化存储器模块的命令序列。 初始化控制单元可以基于配置数据从一组预定义的初始化序列中选择命令序列。
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公开(公告)号：US07155579B1
公开(公告)日：2006-12-26
申请号：US10330991
申请日：2002-12-27
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G11C5/04
摘要： In general, techniques are described for initializing a memory module in accordance with a programmable initialization sequence. A memory controller, for example, includes a programmable computer-readable medium that stores configuration data to control initialization of one or more memory modules. The memory controller includes an initialization control unit that outputs a sequence of commands to initialize the memory modules in accordance with the configuration data. The initialization control unit may select the sequence of commands from a set of predefined initialization sequences based on the configuration data.
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9.发明授权Familial correction with non-familial double bit error detection for directory storage 有权家族性校正，用于目录存储的非家族双位错误检测公开(公告)号：US06973612B1
公开(公告)日：2005-12-06
申请号：US10012638
申请日：2001-11-13
申请人： Eugene A. Rodi
发明人： Eugene A. Rodi
CPC分类号： G06F11/1008
摘要： Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. The application of a code for 128 bit memories is applied to a 20 bit directory store to improve reliability of the directory store memory of the computer system. The code uses ×4 bit DRAM devices organized in a code word of 20 data bit words and 12 check bits. These 12 check bits provide a code capable of 4 bit adjacent error correction within a family (i.e., in a ×4 DRAM) and double bit non-adjacent error detection across the entire 20 bit word, with single bit correction across the word as well. Each device can be though of as a separate family of bits, errors occurring in more than one family are not correctable, but may be detected if only one bit in each of two families is in error. Syndrome generation and regeneration are used together with a specific large code word. Decoding the syndrome and checking it against the regenerated syndrome yield data sufficient for providing the features described.
摘要翻译： 与DRAM芯片故障相关的错误校正和错误检测，特别是适配的服务器内存子系统。 将128位存储器的代码应用于20位目录存储，以提高计算机系统的目录存储存储器的可靠性。 该代码使用组织在20个数据位字和12个校验位的代码字中的x4位DRAM器件。 这12个校验位提供一个能够在整个20位字中进行4位相邻纠错的代码（即，在x4 DRAM中）和双字非相邻错误检测的代码，同时也对该字进行单位校正。 每个设备可以作为一个独立的位系列，发生在多个系列中的错误是不可校正的，但是如果两个系列中的每一个中只有一个位存在错误，则可能被检测到。 综合征生成和再生与特定的大码字一起使用。 对该综合征进行解码并针对再生综合征进行检查，产生足以提供所述特征的数据。
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公开(公告)号：US07093240B1
公开(公告)日：2006-08-15
申请号：US10028152
申请日：2001-12-20
申请人： Eugene A. Rodi , Robert M. Rice
发明人： Eugene A. Rodi , Robert M. Rice
CPC分类号： G06T11/206 , G06F17/5031
摘要： A program and method enables easy creation and manipulation of timing charts. The preferred embodiment employs off-the-shelf commercial software and uses Visual Basic commands to get timing chart drawing commands into the drawing program and out of the spreadsheet program to order the drawing program to produce a displayable and print/plotable file. The user can easily see changes needed and even if they require ripple-through redrawing, because the user manipulates data in the spreadsheet file instead of directly manipulating drawing commands, the spread sheet will carry through ripple-through calculations to modify all lines related to the recalculated data.
摘要翻译： 程序和方法可以轻松创建和操纵时序图。 优选实施例采用现成的商业软件，并且使用Visual Basic命令将时序图绘制命令从绘图程序中取出并且从电子表格程序中排序，以便绘制程序产生可显示和打印/可绘制的文件。 用户可以轻松地查看所需的更改，即使它们需要纹波重绘，因为用户操纵电子表格文件中的数据，而不是直接操作绘图命令，电子表格将进行纹波计算，以修改与 重新计算数据。
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