公开(公告)号：US09529042B2

公开(公告)日：2016-12-27

申请号：US14414991

申请日：2013-07-12

申请人： Mitsubishi Electric Corporation

发明人： Mitsunobu Yoshinaga ,  Tadashi Oi ,  Shinichiro Tsudaka ,  Masayo Nakagawa

IPC分类号： G01R31/28 ,  G01R31/3177 ,  G05B19/05

CPC分类号： G01R31/3177 ,  G05B19/05

摘要： A technique capable of estimating an error point in a logic diagram appropriately. A logic diagram display device includes: a signal line correctness/incorrectness determining unit that determines for each test whether each signal line in the logic diagram is correct or incorrect based on a signal line status value of each signal line and a test table; and a signal line correctness/incorrectness result summarizing unit that calculates a correctness/incorrectness result summarized value of each signal line based on a result of determination about the correctness or incorrectness of each signal line. The logic diagram display device further includes: an error signal line estimating unit that estimates an error in each signal line based on the correctness/incorrectness result summarized value of each signal line; and a display that displays each signal line in the logic diagram in a display style responsive to the error in each signal line.

摘要翻译： 一种能够适当地估计逻辑图中的误差点的技术。 逻辑图显示装置包括：信号线正确性/不正确性确定单元，用于根据每个信号线的信号线状态值和测试表，针对每个测试确定逻辑图中的每条信号线是否正确或不正确; 以及信号线正确性/不正确结果汇总单元，其基于关于每个信号线的正确性或不正确性的结果的结果来计算每个信号线的正确性/不正确结果汇总值。 逻辑图显示装置还包括：误差信号线估计单元，其基于每个信号线的正确性/不正确结果汇总值来估计每条信号线中的误差; 以及显示器，其以响应于每个信号线中的错误的显示样式在逻辑图中显示每个信号线。

公开(公告)号：US20150177322A1

公开(公告)日：2015-06-25

申请号：US14414991

申请日：2013-07-12

申请人： Mitsubishi Electric Corporation

发明人： Mitsunobu Yoshinaga ,  Tadashi Oi ,  Shinichiro Tsudaka ,  Masayo Nakagawa

IPC分类号： G01R31/3177

CPC分类号： G01R31/3177 ,  G05B19/05

摘要： A technique capable of estimating an error point in a logic diagram appropriately. A logic diagram display device includes: a signal line correctness/incorrectness determining unit that determines for each test whether each signal line in the logic diagram is correct or incorrect based on a signal line status value of each signal line and a test table; and a signal line correctness/incorrectness result summarizing unit that calculates a correctness/incorrectness result summarized value of each signal line based on a result of determination about the correctness or incorrectness of each signal line. The logic diagram display device further includes: an error signal line estimating unit that estimates an error in each signal line based on the correctness/incorrectness result summarized value of each signal line; and a display that displays each signal line in the logic diagram in a display style responsive to the error in each signal line.

摘要翻译： 一种能够适当地估计逻辑图中的误差点的技术。 逻辑图显示装置包括：信号线正确性/不正确性确定单元，用于根据每个信号线的信号线状态值和测试表，针对每个测试确定逻辑图中的每条信号线是否正确或不正确; 以及信号线正确性/不正确结果汇总单元，其基于关于每个信号线的正确性或不正确性的结果的结果来计算每个信号线的正确性/不正确结果汇总值。 逻辑图显示装置还包括：误差信号线估计单元，其基于每个信号线的正确性/不正确结果汇总值来估计每条信号线中的误差; 以及显示器，其以响应于每个信号线中的错误的显示样式在逻辑图中显示每个信号线。