公开(公告)号：US06870771B2

公开(公告)日：2005-03-22

申请号：US10200773

申请日：2002-07-24

申请人： Mitsuhiro Tomoeda ,  Atsushi Ohba ,  Toshimasa Makino

发明人： Mitsuhiro Tomoeda ,  Atsushi Ohba ,  Toshimasa Makino

IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34

CPC分类号： G11C16/3445 ,  G11C16/14 ,  G11C16/16 ,  G11C16/344

摘要： In a memory block that is to be subjected to an erasure operation, voltage of the ground level is selectively supplied to only one word line. By applying an erasure pulse to a source line, memory cell transistors have their threshold voltages shifted. As to another word line, a pulse of a positive voltage is supplied in synchronization to the application of an erasure pulse to the source line. Another group of memory cell transistors do not have their threshold voltages shifted.

摘要翻译： 在要进行擦除操作的存储器块中，选择地仅将一个字线提供接地电平的电压。 通过对源极线施加擦除脉冲，存储单元晶体管的阈值电压偏移。 对于另一个字线，同步地提供正电压的脉冲以向消除线施加擦除脉冲。 另一组存储单元晶体管不具有偏移其阈值电压。