公开(公告)号：US07281113B2

公开(公告)日：2007-10-09

申请号：US11140944

申请日：2005-06-01

申请人： Mitsutoshi Fujita ,  Kenji Tsutsumi

发明人： Mitsutoshi Fujita ,  Kenji Tsutsumi

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F8/65

摘要： A microcomputer comprises a CPU; a nonvolatile memory; a plurality of volatile memories; a system bus; a program transfer bus; a program transfer section; an address conversion section; and a voltage detection section. The volatile memories include a plurality of memories switchable to be used as transfer and execution memories in accordance with a program execution state by the CPU. Where the voltage detected by the voltage detection section is lower than a first voltage, the program transfer section transfers the part of the program stored in the nonvolatile memory to the transfer memory, and the address conversion section converts an address in the nonvolatile memory output from the CPU into an address in the execution memory.

摘要翻译： 微型计算机包括CPU; 非易失性存储器; 多个易失性存储器; 系统总线 程序传输总线; 程序转移部分; 地址转换部分; 和电压检测部。 易失性存储器包括可根据CPU的程序执行状态切换成用作传送和执行存储器的多个存储器。 在由电压检测部分检测到的电压低于第一电压的情况下，程序传送部分将存储在非易失性存储器中的程序的一部分传送到传送存储器，并且地址转换部分转换从非易失性存储器输出的地址 CPU进入执行存储器中的一个地址。

公开(公告)号：US20050268069A1

公开(公告)日：2005-12-01

申请号：US11140944

申请日：2005-06-01

申请人： Mitsutoshi Fujita ,  Kenji Tsutsumi

发明人： Mitsutoshi Fujita ,  Kenji Tsutsumi

IPC分类号： G06F15/78 ,  G06F9/26 ,  G06F9/445 ,  G06F12/00

CPC分类号： G06F8/65

摘要： A microcomputer comprises a CPU; a nonvolatile memory; a plurality of volatile memories; a system bus; a program transfer bus; a program transfer section; an address conversion section; and a voltage detection section. The volatile memories include a plurality of memories switchable to be used as transfer and execution memories in accordance with a program execution state by the CPU. Where the voltage detected by the voltage detection section is lower than a first voltage, the program transfer section transfers the part of the program stored in the nonvolatile memory to the transfer memory, and the address conversion section converts an address in the nonvolatile memory output from the CPU into an address in the execution memory.

摘要翻译： 微型计算机包括CPU; 非易失性存储器 多个易失性存储器; 系统总线 程序传输总线; 程序转移部分; 地址转换部分; 和电压检测部。 易失性存储器包括可根据CPU的程序执行状态切换成用作传送和执行存储器的多个存储器。 在由电压检测部分检测到的电压低于第一电压的情况下，程序传送部分将存储在非易失性存储器中的程序的一部分传送到传送存储器，并且地址转换部分转换从非易失性存储器输出的地址 CPU进入执行存储器中的一个地址。

公开(公告)号：US07791519B2

公开(公告)日：2010-09-07

申请号：US12293910

申请日：2007-03-22

申请人： Kazuo Matsukawa ,  Mitsutoshi Fujita

发明人： Kazuo Matsukawa ,  Mitsutoshi Fujita

IPC分类号： H03M1/66

CPC分类号： G01R31/31932 ,  G01R31/3167

摘要： In a pass/fail judgment test for a semiconductor IC having plural DACs, there is a problem that the test time is undesirably increased due to an increase on the number of DACs or an increase in resolution.When testing two DACs, i.e., DAC1 and DAC2, a control unit (170) alternately increases the digital input values of the DAC1 and DAC2, whereby the output of a comparator 1 to which the analog output values of the DAC1 and DAC2 are inputted repeats inversion between “0” and “1”. It is judged whether the DACs are conforming or not by judging with a judgment unit (180) whether the output pattern of the comparator 1 matches an expected value or not.

摘要翻译： 在具有多个DAC的半导体IC的通过/失败判定测试中，存在由于DAC数量的增加或分辨率的增加而导致的测试时间不期望地增加的问题。 当测试两个DAC（即DAC1和DAC2）时，控制单元（170）交替地增加DAC1和DAC2的数字输入值，由此重复输入DAC1和DAC2的模拟输出值的比较器1的输出 “0”和“1”之间的反转。 通过判断单元（180）判断比较器1的输出模式是否与期望值相匹配来判断DAC是否符合要求。

公开(公告)号：US20090128382A1

公开(公告)日：2009-05-21

申请号：US12293910

申请日：2007-03-22

申请人： Kazuo Matsukawa ,  Mitsutoshi Fujita

发明人： Kazuo Matsukawa ,  Mitsutoshi Fujita

IPC分类号： H03M1/10

CPC分类号： G01R31/31932 ,  G01R31/3167

摘要： In a pass/fail judgment test for a semiconductor IC having plural DACs, there is a problem that the test time is undesirably increased due to an increase on the number of DACs or an increase in resolution.When testing two DACs, i.e., DAC1 and DAC2, a control unit (170) alternately increases the digital input values of the DAC1 and DAC2, whereby the output of a comparator 1 to which the analog output values of the DAC1 and DAC2 are inputted repeats inversion between “0” and “1”. It is judged whether the DACs are conforming or not by judging with a judgment unit (180) whether the output pattern of the comparator 1 matches an expected value or not.

摘要翻译： 在具有多个DAC的半导体IC的通过/失败判定测试中，存在由于DAC数量的增加或分辨率的增加而导致测试时间不期望地增加的问题。 当测试两个DAC（即DAC1和DAC2）时，控制单元（170）交替地增加DAC1和DAC2的数字输入值，由此重复输入DAC1和DAC2的模拟输出值的比较器1的输出 “0”和“1”之间的反转。 通过判断单元（180）判断比较器1的输出模式是否与期望值相匹配来判断DAC是否符合要求。

公开(公告)号：US07148135B2

公开(公告)日：2006-12-12

申请号：US10815690

申请日：2004-04-02

申请人： Mitsutoshi Fujita ,  Shuji Kondo

发明人： Mitsutoshi Fujita ,  Shuji Kondo

IPC分类号： H01L21/44

CPC分类号： G06F17/505 ,  G06F17/5068

摘要： A branching point on a wire is detected in the layout results S101. A delay amount of a route with a dummy buffer being inserted on a wire subsequent to the branching point S102 and that of the route without a dummy buffer being inserted are then calculated S103. Based on the delay amounts, an insertion point at which a load-dividing buffer is to be inserted is determined S104. On condition that a load-dividing buffer is to be inserted at the insertion point, the drive capability of a driving cell preceding the insertion point is calculated so that timing constraints are satisfied S105. Then, after it is confirmed that a load-dividing buffer is insertable at the determined insertion point S106, processes of placing a load-dividing buffer, changing the drive capability of the driving cell, and changing wiring information are performed on the layout results S107.

摘要翻译： 在布局结果S101中检测到线上的分支点。 然后，计算在分支点S102之后的导线上插入具有虚拟缓冲器的路径的延迟量和未插入虚拟缓冲器的路线的延迟量。 基于延迟量，确定插入加载分割缓冲器的插入点S 104。 在插入点插入加载分割缓冲器的情况下，计算出插入点之前的驱动单元的驱动能力，使得时序约束得到满足S105。 然后，在确定了在确定的插入点S106上插入负载分配缓冲器之后，对布局结果执行放置加载分割缓冲器，改变驱动单元的驱动能力以及改变布线信息的处理 S 107。

公开(公告)号：US08085012B2

公开(公告)日：2011-12-27

申请号：US12133911

申请日：2008-06-05

申请人： Mitsutoshi Fujita

发明人： Mitsutoshi Fujita

IPC分类号： G05F1/00

CPC分类号： G01D5/14

摘要： In a sensor driving/measuring system, specifications required by a sensor which requires a high applied voltage are implemented with const increase suppressed. A semiconductor integrated circuit for use in a sensor driving/measuring system driven by a battery includes: a sensor driver for outputting a given voltage to be applied to a sensor; a measuring circuit for receiving and measuring a voltage obtained, through current-voltage conversion, from a current generated in the sensor; and a booster. The booster boosts a given pre-boost voltage to obtain a boosted voltage and supplies the boosted voltage as a power supply voltage to the sensor driver and the measuring circuit.

摘要翻译： 在传感器驱动/测量系统中，需要增加高电压的传感器所要求的规格被抑制地增加。 一种用于由电池驱动的传感器驱动/测量系统的半导体集成电路包括：用于输出要施加到传感器的给定电压的传感器驱动器; 测量电路，用于通过电流 - 电压转换从所述传感器中产生的电流接收和测量所获得的电压; 和助推器。 升压器升压给定的预升压电压以获得升压电压，并将提升的电压作为电源电压提供给传感器驱动器和测量电路。

公开(公告)号：US20090021226A1

公开(公告)日：2009-01-22

申请号：US12133911

申请日：2008-06-05

申请人： Mitsutoshi Fujita

发明人： Mitsutoshi Fujita

IPC分类号： G05F1/10

CPC分类号： G01D5/14

摘要： In a sensor driving/measuring system, specifications required by a sensor which requires a high applied voltage are implemented with const increase suppressed. A semiconductor integrated circuit for use in a sensor driving/measuring system driven by a battery includes: a sensor driver for outputting a given voltage to be applied to a sensor; a measuring circuit for receiving and measuring a voltage obtained, through current-voltage conversion, from a current generated in the sensor; and a booster. The booster boosts a given pre-boost voltage to obtain a boosted voltage and supplies the boosted voltage as a power supply voltage to the sensor driver and the measuring circuit.

摘要翻译： 在传感器驱动/测量系统中，需要增加高电压的传感器所要求的规格被抑制地增加。 一种用于由电池驱动的传感器驱动/测量系统的半导体集成电路包括：用于输出要施加到传感器的给定电压的传感器驱动器; 测量电路，用于通过电流 - 电压转换从所述传感器中产生的电流接收和测量所获得的电压; 和助推器。 升压器升压给定的预升压电压以获得升压电压，并将提升的电压作为电源电压提供给传感器驱动器和测量电路。