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48 条记录 (耗时 0.076 秒)

    Reconfigurable operation apparatus
    1.
    发明申请
    Reconfigurable operation apparatus 有权
    可重构操作装置

    公开(公告)号：US20060010306A1

    公开(公告)日：2006-01-12

    申请号：US11077561

    申请日：2005-03-11

    申请人： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

    发明人： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

    IPC分类号： G06F15/00

    CPC分类号： G06F15/8007

    摘要： A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

    摘要翻译： 可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。 配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

    Array processor having reconfigurable data transfer capabilities
    2.
    发明授权
    Array processor having reconfigurable data transfer capabilities 有权
    阵列处理器具有可重新配置的数据传输能力

    公开(公告)号：US07774580B2

    公开(公告)日：2010-08-10

    申请号：US11077561

    申请日：2005-03-11

    申请人： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

    发明人： Miyoshi Saito ,  Hisanori Fujisawa ,  Hideki Yoshizawa ,  Tetsu Tanizawa ,  Ichiro Kasama ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa ,  Shiro Uriu ,  Mitsuharu Wakayoshi

    IPC分类号： G06F15/00 ,  G06F15/76

    CPC分类号： G06F15/8007

    摘要： A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

    摘要翻译： 可重构操作装置由能够通过使用一段给定的第一配置数据并且彼此同时操作的多个操作单元组成，能够重新配置自身; RAMs 构成操作装置所需的各种处理器元件; 互连所述操作单元，所述RAM和所述不同处理器元件的资源间网络，以与所述资源的位置和种类无关的统一传送时间在连接到其之间的资源之间执行数据传输，并且可通过使用给定的第二配置数据来重新配置; 以及存储第一和第二配置数据的配置存储器。 配置数据从外部存储装置加载到配置存储器上，并且基于从多个操作单元可获得的数据，将第一和第二配置数据以适当的顺序和定时提供给可重构处理器资源。

    Semiconductor device
    9.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060004979A1

    公开(公告)日：2006-01-05

    申请号：US11167310

    申请日：2005-06-28

    申请人： Tetsuo Kawano ,  Hiroshi Furukawa ,  Ichiro Kasama ,  Kazuaki Imafuku ,  Toshiaki Suzuki ,  Miyoshi Saito

    发明人： Tetsuo Kawano ,  Hiroshi Furukawa ,  Ichiro Kasama ,  Kazuaki Imafuku ,  Toshiaki Suzuki ,  Miyoshi Saito

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0646 ,  G06F13/1694 ,  G06F15/7867

    摘要： A semiconductor device includes a plurality of memories, a sequencer which outputs configuration information, and a memory reconfiguring circuit which reconfigures the memory area in accordance with the configuration information supplied from the sequencer. Since the memory reconfiguring circuit dynamically changes the allocation of the memories, it is possible to reconfigure the memory configuration and freely change the memory size in accordance with the purpose of use.

    摘要翻译： 半导体器件包括多个存储器，输出配置信息的定序器和根据从定序器提供的配置信息重新配置存储器区域的存储器重配置电路。 由于存储器重新配置电路动态地改变存储器的分配，所以可以根据使用目的重新配置存储器配置并自由地改变存储器大小。

    Reconfigurable processor and semiconductor device
    10.
    发明申请
    Reconfigurable processor and semiconductor device 审中-公开
    可重配置的处理器和半导体器件

    公开(公告)号：US20050289327A1

    公开(公告)日：2005-12-29

    申请号：US11037049

    申请日：2005-01-19

    申请人： Ichiro Kasama ,  Toshiaki Suzuki ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa

    发明人： Ichiro Kasama ,  Toshiaki Suzuki ,  Tetsuo Kawano ,  Kazuaki Imafuku ,  Hiroshi Furukawa

    IPC分类号： G06F9/30 ,  G06F9/46 ,  G06F15/00

    CPC分类号： G06F9/461 ,  G06F9/3885 ,  G06F9/3897

    摘要： A reconfigurable processor in which an application can be switched more freely. A switching condition associating section associates output from a plurality of arithmetic and logic unit modules used as switching conditions for switching the operation of an arithmetic and logic unit group with a plurality of states indicative of switching condition codes. When a switching condition code output section decides that a switching condition comes into existence on the basis of the output from the plurality of arithmetic and logic unit modules set as the switching conditions, the switching condition code output section outputs a switching condition code corresponding to the switching condition which comes into existence. When a sequencer accepts the switching condition code, the sequencer switches the arithmetic and logic unit group to a state corresponding to the switching condition code.

    摘要翻译： 可重新配置的处理器，其中可以更自由地切换应用。 切换条件关联部分将用作切换条件的多个算术和逻辑单元模块的输出相关联，用于切换算术和逻辑单元组的操作与表示切换条件代码的多个状态。 当切换条件代码输出部根据设定为切换条件的多个算术逻辑单元模块的输出决定切换条件成立时，切换条件代码输出部输出对应于 切换条件成立。 当定序器接受切换条件代码时，定序器将算术和逻辑单元组切换到与切换条件代码相对应的状态。