公开(公告)号：US08842721B1

公开(公告)日：2014-09-23

申请号：US13244599

申请日：2011-09-25

申请人： Mohammad Shahanshah Akhter ,  Barry Everett Wood ,  Randy May

发明人： Mohammad Shahanshah Akhter ,  Barry Everett Wood ,  Randy May

IPC分类号： H03H7/30

CPC分类号： H04L25/0307 ,  H04L25/03885 ,  H04L25/4908 ,  H04L2025/03592

摘要： A Method and Apparatus for Channel Equalization in High Speed S-RIO based Communication Systems have been disclosed. By adjusting equalizer coefficients based on 8B10B error counts and an error threshold, a receiver may be dynamically adjusted. By adjusting transmitter pre-emphasis based on 8B10B error counts and an error threshold, a transmitter may be dynamically adjusted. Both the transmitter and receiver may be adjusted dynamically based on 8B10B error counts and different error thresholds.

摘要翻译： 已经公开了用于基于高速S-RIO的通信系统中的信道均衡的方法和装置。 通过调整基于8B10B误差计数和误差阈值的均衡器系数，可以动态地调整接收器。 通过基于8B10B误差计数和误差阈值调整发射机预加重，可以动态调整发射机。 可以根据8B10B错误计数和不同的错误阈值动态调整发送器和接收器。

公开(公告)号：US06393590B1

公开(公告)日：2002-05-21

申请号：US09218361

申请日：1998-12-22

申请人： Barry Everett Wood ,  Brian Baker

发明人： Barry Everett Wood ,  Brian Baker

IPC分类号： G06F1114

CPC分类号： G06F11/0757 ,  G06F11/0724

摘要： The present invention relates to a method and apparatus for ensuring fault detection and system recovery in a multiprocessor computing system. This system comprises a multitude of processing element modules, input/output processor modules and shared memory modules. Each module within the system includes an identical period sanity timer capable to reset the module once a predetermined limit count is reached. If a global clear signal is not received from the operating system scheduler by all modules prior to the expiry of the sanity timers, a system-wide reset is effected. Each processing element module within the system further includes a watchdog timer capable to reset the module once a predetermined limit count is reached. If a process is not run by the operating system scheduler on the processing element before the expiry of the watchdog timer, effectively clearing the watchdog timer, the processing element is reset and removed from service.

摘要翻译： 本发明涉及一种用于确保多处理器计算系统中的故障检测和系统恢复的方法和装置。 该系统包括多个处理元件模块，输入/输出处理器模块和共享存储器模块。 系统中的每个模块都包含一个相同的周期卫生定时器，一旦达到预定的限制计数器就能复位模块。 如果在理智定时器到期之前，所有模块都没有从操作系统调度器接收到全局清除信号，则会进行系统范围的复位。 系统内的每个处理元件模块还包括看门狗定时器，一旦达到预定的限制值就能复位模块。 如果在看门狗定时器期满之前，处理元件上的操作系统调度器不运行进程，则有效地清除看门狗定时器，处理元件被重置并从服务中移除。