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23 条记录 (耗时 0.018 秒)

    CANCELING SELF-JAMMER AND INTERFERING SIGNALS IN AN RFID SYSTEM
    1.
    发明申请
    CANCELING SELF-JAMMER AND INTERFERING SIGNALS IN AN RFID SYSTEM 失效
    在RFID系统中取消自拍和干扰信号

    公开(公告)号：US20090036082A1

    公开(公告)日：2009-02-05

    申请号：US11830914

    申请日：2007-07-31

    申请人： Mohammed Sajid ,  Scott Chiu

    发明人： Mohammed Sajid ,  Scott Chiu

    IPC分类号： H04B1/10

    CPC分类号： H04B1/525 ,  G06K7/0008

    摘要： Briefly, in accordance with one or more embodiments, a method and device capable of canceling self-jammer and one or more other interfering signals in an radio frequency identification system or the like is disclosed.

    摘要翻译： 简而言之，根据一个或多个实施例，公开了能够在射频识别系统等中抵消自干扰和一个或多个其它干扰信号的方法和装置。

    Canceling self-jammer and interfering signals in an RFID system
    2.
    发明授权
    Canceling self-jammer and interfering signals in an RFID system 失效
    取消RFID系统中的自干扰和干扰信号

    公开(公告)号：US08000674B2

    公开(公告)日：2011-08-16

    申请号：US11830914

    申请日：2007-07-31

    申请人： Mohammed Sajid ,  Scott Chiu

    发明人： Mohammed Sajid ,  Scott Chiu

    IPC分类号： H04B1/10

    CPC分类号： H04B1/525 ,  G06K7/0008

    摘要： Briefly, in accordance with one or more embodiments, a method and device capable of canceling self-jammer and one or more other interfering signals in an radio frequency identification system or the like is disclosed.

    摘要翻译： 简而言之，根据一个或多个实施例，公开了能够在射频识别系统等中抵消自干扰和一个或多个其它干扰信号的方法和装置。

    RECONFIGURABLE LOAD-REDUCED MEMORY BUFFER
    5.
    发明申请
    RECONFIGURABLE LOAD-REDUCED MEMORY BUFFER 审中-公开
    可重新加载减少的内存缓冲区

    公开(公告)号：US20140313838A1

    公开(公告)日：2014-10-23

    申请号：US14173221

    申请日：2014-02-05

    申请人： Scott Chiu ,  Mohamed Arafa

    发明人： Scott Chiu ,  Mohamed Arafa

    IPC分类号： G11C7/10

    CPC分类号： G11C7/10 ,  G06F1/3275 ,  G06F1/3287 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/14

    摘要： A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In one example, the memory module also includes a registered buffer having an address bus interface, where the switch may selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface.

    摘要翻译： 存储器模块可以包括具有数据总线接口的数据缓冲器和耦合到数据缓冲器的动态随机存取存储器（DRAM）。 存储器模块还可以包括与数据缓冲器并联连接的开关，其中开关可以有选择地绕过数据缓冲器。 在一个示例中，存储器模块还包括具有地址总线接口的注册缓冲器，其中交换机可以基于经由地址总线接口从地址总线获得的程序信号选择性地旁路数据缓冲器。

    Filter scheme for receiver
    6.
    发明授权
    Filter scheme for receiver 失效
    接收机滤波器方案

    公开(公告)号：US07742751B2

    公开(公告)日：2010-06-22

    申请号：US11613986

    申请日：2006-12-20

    申请人： Scott Chiu ,  Issy Kipnis ,  Jan Rapp ,  David Westberg

    发明人： Scott Chiu ,  Issy Kipnis ,  Jan Rapp ,  David Westberg

    IPC分类号： H04B1/26

    CPC分类号： H04B1/30

    摘要： Provided are a method, system, and device directed to a receive path for a node in a communication system such as a Radio Frequency Identification (RFID) system. In one aspect, the receive path includes a filter operable in multiple modes and configurable to have different bandwidths in the various modes of operation. For example, in one mode, the filter samples a DC component while configured to have a relatively wide bandwidth. As another example, the filter may be operated in another mode to hold the sampled DC component while the filter is configured to have a zero or close to zero bandwidth. As yet another example, the filter may be operated in still another mode to filter received signals and cancel the sampled DC offset from the received signals while configured to have a relatively narrow bandwidth. Additional embodiments are described and claimed.

    摘要翻译： 提供了一种针对诸如射频识别（RFID）系统的通信系统中的节点的接收路径的方法，系统和设备。 在一个方面，接收路径包括可在多种模式下操作并可配置为在各种操作模式中具有不同带宽的滤波器。 例如，在一种模式中，滤波器对DC分量进行采样，同时配置为具有相对较宽的带宽。 作为另一示例，滤波器可以在另一模式下操作以保持采样的DC分量，同时滤波器被配置为具有零或接近零带宽。 作为另一示例，滤波器可以在另一模式下操作以对接收到的信号进行滤波，并且在被配置为具有相对窄的带宽的同时从接收到的信号中取消采样的DC偏移。 描述和要求保护附加的实施例。

    Error correction method and apparatus for data transmission system
    7.
    发明授权
    Error correction method and apparatus for data transmission system 失效

    公开(公告)号：US07035365B2

    公开(公告)日：2006-04-25

    申请号：US10001712

    申请日：2002-03-11

    申请人： Hiroshi Takatori ,  James M. Little ,  Scott Chiu

    发明人： Hiroshi Takatori ,  James M. Little ,  Scott Chiu

    IPC分类号： H04L7/00 ,  H04L7/02

    CPC分类号： H04L1/205

    摘要： A receiver involved in high-speed data transmission includes a decision system. The decision system calculates a value of an input signal and holds the value as a tentative value. The decision system calculates an error value, amplifies the error value, and holds the amplified error value as a corrected value. The decision system determines whether the amplified error value is within a marginal range. The decision system also determines whether adjacent values to the value indicate the input signal was in transition from a positive to negative state, or a negative to positive state. If the amplified error values is within a marginal range and the input signal was in transition from a positive to negative state, or a negative to positive state, then the decision system overrides the tentative value with the corrected value.

    Systems and methods for RF communication between processors
    8.
    发明授权
    Systems and methods for RF communication between processors 有权
    处理器之间RF通信的系统和方法

    公开(公告)号：US08768411B2

    公开(公告)日：2014-07-01

    申请号：US11241067

    申请日：2005-09-30

    申请人： Keith R. Tinsley ,  Scott Chiu

    发明人： Keith R. Tinsley ,  Scott Chiu

    IPC分类号： H04M1/00

    CPC分类号： G06F13/4004

    摘要： Embodiments include systems and methods for integration of RF components onto a single die with functional processing circuitry. For example, one integrated circuit may comprise multiple processors that can communicate there between by way of Radio Frequency (RF) transmission. The processors may also communicate with slave devices by way of radio frequency. Transmission and reception may be at frequencies in a band hitherto unused in computing devices and their peripherals.

    摘要翻译： 实施例包括用于将RF组件集成到具有功能处理电路的单个管芯上的系统和方法。 例如，一个集成电路可以包括可以通过射频（RF）传输之间在那里通信的多个处理器。 处理器还可以通过无线电频率与从设备进行通信。 传输和接收可以是在计算设备及其外围设备中迄今使用的频带中的频率。

    Reconfigurable load-reduced memory buffer
    9.
    发明授权
    Reconfigurable load-reduced memory buffer 有权
    可重构减载内存缓冲区

    公开(公告)号：US08688901B2

    公开(公告)日：2014-04-01

    申请号：US12632919

    申请日：2009-12-08

    申请人： Scott Chiu ,  Mohamed Arafa

    发明人： Scott Chiu ,  Mohamed Arafa

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G11C7/10 ,  G06F1/3275 ,  G06F1/3287 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/14

    摘要： A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In one example, the memory module also includes a registered buffer having an address bus interface, where the switch may selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface.

    摘要翻译： 存储器模块可以包括具有数据总线接口的数据缓冲器和耦合到数据缓冲器的动态随机存取存储器（DRAM）。 存储器模块还可以包括与数据缓冲器并联连接的开关，其中开关可以有选择地绕过数据缓冲器。 在一个示例中，存储器模块还包括具有地址总线接口的注册缓冲器，其中交换机可以基于经由地址总线接口从地址总线获得的程序信号选择性地旁路数据缓冲器。