公开(公告)号：US5826048A

公开(公告)日：1998-10-20

申请号：US790303

申请日：1997-01-31

Applicant: Morgan James Dempsey ,  Rajeev Jayavant

Inventor： Morgan James Dempsey ,  Rajeev Jayavant

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4018

Abstract: A Mini-PCI (MPCI) interface, and associated circuits and methods are provided for connecting a Peripheral Component Interconnect (PCI) device to one or more external devices. The MPCI interface, circuits and methods provide for a substantial if not full implementation of a PCI Local Bus without requiring the standard number of pins, traces, or signals. The MPCI interface includes a PCI/MPCI bridge connected between a PCI bus and to up to eight external devices in the form of MPCI devices and linear memory devices. The PCI/MPCI bridge is capable of receiving an incoming PCI transaction and multiplexing some of its signals together to create a corresponding incoming MPCI transaction. This incoming MPCI transaction may then be passed over an MPCI bus, having fewer lines and optimally operating at a higher frequency, the external devices. The process is reversed for outgoing transactions, i.e., the MPCI transactions are de-multiplexed to create PCI transactions. Additionally, the MPCI interface may also be configured to provide for direct access to linearly addressed memory devices without adding a PCI interface to the external interface. The invention may be implemented through integrated circuitry and/or computer implemented instructions, and may be included within a personal computer.

Abstract translation: 提供Mini-PCI（MPCI）接口以及相关的电路和方法，用于将外围组件互连（PCI）设备连接到一个或多个外部设备。 MPCI接口，电路和方法在不需要标准数量的引脚，迹线或信号的情况下提供完全实现的PCI本地总线。 MPCI接口包括连接在PCI总线和MPCI设备和线性存储器设备形式的多达八个外部设备之间的PCI / MPCI桥接器。 PCI / MPCI网桥能够接收进入的PCI事务并将其一些信号复用在一起以创建相应的传入MPCI事务。 然后，该传入的MPCI事务可以通过MPCI总线传递，具有较少的线路并且以更高的频率最佳地操作外部设备。 对于输出事务，该过程是反转的，即MPCI事务被解复用以创建PCI事务。 此外，MPCI接口还可以被配置为提供对线性寻址的存储器设备的直接访问，而不向外部接口添加PCI接口。 本发明可以通过集成电路和/或计算机实现的指令来实现，并且可以包括在个人计算机内。

公开(公告)号：US5717875A

公开(公告)日：1998-02-10

申请号：US532936

申请日：1995-09-22

Applicant: Huzefa H. Cutlerywala ,  Rajeev Jayavant ,  Judson A. Lehman

Inventor： Huzefa H. Cutlerywala ,  Rajeev Jayavant ,  Judson A. Lehman

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: An improved bus architecture is provided in which the bus connects a single master to multiple targets including one primary target. Bus usage is predominately between the master and one primary target at a very high data transfer rate. Traffic between the master and other secondary targets has a much lower bandwidth requirement. The bus uses a single frequency clock for transfers involving the primary target and transfers involving the secondary targets. In accordance with one embodiment of the invention, the master is connected to the primary high bandwidth target using a high speed protocol and separate read and write data paths which are always driven (i.e., never tri-stated). Always driving the high speed data paths avoids the increased area and decreased performance that would be entailed by adding additional gating. The lower bandwidth targets are supported on a single bi-directional data path to minimize area. This lower bandwidth path has a different protocol and is only activated upon command from the master in order to reduce power dissipation. This construction is different from a bus bridge in that the master specifically initiates activity on the low bandwidth bus, based on the target's address. The master knows which path will process a cycle, and cycles are completed differently for each path.

Abstract translation: 提供了一种改进的总线架构，其中总线将单个主机连接到包括一个主要目标的多个目标。 在非常高的数据传输速率下，总线使用主要在主机和主要目标之间。 主控和其他辅助目标之间的流量具有低得多的带宽要求。 总线使用单个频率时钟进行涉及主要目标的转移和涉及次要目标的转移。 根据本发明的一个实施例，主器件使用高速协议和始终被驱动（即，从不三态）的单独的读和写数据路径连接到主高带宽目标。 始终驾驶高速数据路径可避免增加额外门控所带来的面积增加和性能下降。 在单个双向数据路径上支持较低带宽目标，以最小化面积。 该较低带宽路径具有不同的协议，并且仅在来自主机的命令时被激活，以便降低功耗。 这种结构不同于总线桥，因为主机根据目标地址专门在低带宽总线上启动活动。 主人知道哪个路径将处理一个周期，并且每个路径的周期完成不同。

公开(公告)号：US10817043B2

公开(公告)日：2020-10-27

申请号：US13191364

申请日：2011-07-26

Applicant: Rajeev Jayavant ,  Thomas E. Dewey ,  David Wyatt

Inventor： Rajeev Jayavant ,  Thomas E. Dewey ,  David Wyatt

IPC: G06T1/00 ,  G06F1/3234

Abstract: A technique is disclosed for a graphics processing unit (GPU) to enter and exit a power saving deep sleep mode. The technique involves preserving processing state within local memory by configuring the local memory to operate in a self-refresh mode while the GPU is powered off for deep sleep. An interface circuit coupled to the local memory is configured to prevent spurious GPU signals from disrupting proper self-refresh of the local memory. Spurious GPU signals may result from GPU power down and GPU power up events associated with the GPU entering and exiting the deep sleep mode.

公开(公告)号：US06718439B1

公开(公告)日：2004-04-06

申请号：US09872313

申请日：2001-06-01

Applicant: Rajeev Jayavant

Inventor： Rajeev Jayavant

IPC: G06F1200

CPC classification number: G06F12/0864 ,  G06F12/0897 ,  G06F2212/6082

Abstract: An N-way set associative virtual victim cache in which cache accesses are automatically directed only to the data array in the most recently used way. The cache memory comprises: 1) N ways, each of the N ways comprising a data array capable of storing L cache lines and a tag array capable of storing L address tags, each of the L address tags associated with one of the L cache lines; and 2) address decoding circuitry capable of receiving an incoming memory address and accessing a target cache line corresponding to the incoming memory address only in a most recently used one of the N ways.

Abstract translation: 一种N路组关联虚拟受害者缓存，其中高速缓存访​​问仅以最近使用的方式自动地引导到数据阵列。 高速缓冲存储器包括：1）N路，N路中的每一条包括能够存储L个高速缓存行的数据阵列和能够存储L个地址标签的标签阵列，每个L个地址标签与L个高速缓存行之一相关联 ; 以及2）地址解码电路，其能够仅在最近使用的N种方式之一中接收输入存储器地址并且访问对应于输入存储器地址的目标高速缓存行。

公开(公告)号：US07136071B1

公开(公告)日：2006-11-14

申请号：US10874832

申请日：2004-06-23

Applicant: Walter E. Donovan ,  Rajeev Jayavant

Inventor： Walter E. Donovan ,  Rajeev Jayavant

IPC: G09G5/00 ,  G06T15/60 ,  G06T17/00 ,  G06K9/40

CPC classification number: G06T15/04

Abstract: An apparatus and method for using non-power of two texture maps is described. Normalized texture map coordinates such as s and t are converted from a floating point format to a fixed point format and wrapping operations are performed to produce unnormalized texture map coordinates such as u and v corresponding to non-power of two texture maps.

Abstract translation: 描述了使用两个纹理贴图的非幂的装置和方法。 归一化纹理映射坐标如s和t从浮点格式转换为固定点格式，并执行包装操作，以产生非标准纹理贴图坐标，例如对应于两个纹理贴图的非幂的u和v。

公开(公告)号：US06967659B1

公开(公告)日：2005-11-22

申请号：US09648173

申请日：2000-08-25

Applicant: Rajeev Jayavant ,  David W. Nuechterlein

Inventor： Rajeev Jayavant ,  David W. Nuechterlein

IPC: G06T1/20 ,  G06T15/00 ,  H04N7/26 ,  H04N7/36

CPC classification number: H04N19/42 ,  G06T1/20 ,  G06T15/005 ,  G06T2200/28 ,  H04N19/51

Abstract: The present invention introduces circuitry and systems for performing two-dimensional motion compensation using a three-dimensional pipeline, as well as methods of operating the same. According to an exemplary embodiment, image processing circuitry is provided and includes both a two-dimensional image pipeline, which is operable to process two dimensional image data to generate successive two-dimensional image frames, and a three-dimensional image pipeline, which is operable to process three-dimensional image data to render successive three-dimensional image frames. The image processing circuitry further includes dual mode sub-processing circuitry, which is associated with each of the two- and three-dimensional image pipelines. The dual mode sub-processing circuitry is operable to perform motion compensation operations associated with the two-dimensional image pipeline in one mode and to perform rasterization operations associated the three-dimensional image pipeline in another mode.

Abstract translation: 本发明引入了使用三维流水线执行二维运动补偿的电路和系统，以及其操作方法。 根据示例性实施例，提供图像处理电路，并且包括可操作以处理二维图像数据以生成连续的二维图像帧的二维图像流水线，以及可操作的三维图像流水线 以处理三维图像数据以呈现连续的三维图像帧。 图像处理电路还包括双模式子处理电路，其与二维和三维图像管线中的每一个相关联。 双模式子处理电路可操作以在一种模式中执行与二维图像流水线相关联的运动补偿操作，并且执行与另一模式中的三维图像流水线相关联的光栅化操作。

公开(公告)号：US06434688B1

公开(公告)日：2002-08-13

申请号：US08530617

申请日：1995-09-20

Applicant: William Desi Rhoden ,  Rajeev Jayavant

Inventor： William Desi Rhoden ,  Rajeev Jayavant

IPC: G06F1500

CPC classification number: G06F12/0223 ,  G06F12/02

Abstract: The present invention provides a low-cost computer system which includes a single sharable block of memory that can be independently accessible as graphics memory or main store system memory without performance degradation. Because the “appetite” for main system memory (unlike that of a display memory) is difficult to satisfy, the memory can be addressed by reallocating an unused portion of a display memory for system memory use. Reallocation of the unused display memory alleviates any need to oversize the display memory, yet realizes the cost effectiveness of using readily available memory sizes. Further, reallocation of the graphics memory avoids any need to separately consider both the system memory and the display memory in accommodating worst case operational requirements. In accordance with additional embodiments, improved efficiency of operation can be achieved to enhance concurrency between plural banks of memory when expansion memory is included. The addressable locations of the expansion memory can be mapped to the bottom of the available system address space, and addressable locations of any prior base system memory are moved above the expansion memory space.

Abstract translation: 本发明提供了一种低成本计算机系统，其包括单个共享存储器块，其可以作为图形存储器或主存储系统存储器独立地访问，而不会降低性能。 由于主系统存储器（与显示存储器不同）的“胃口”难以满足，所以可以通过重新分配用于系统存储器使用的显示存储器的未使用部分来解决存储器。 未使用的显示存储器的重新分配减轻了对显示存储器进行超大尺寸的任何需求，但是实现了使用容易获得的存储器大小的成本效益。 此外，重新分配图形存储器避免了在适应最坏情况操作要求时单独考虑系统存储器和显示存储器的任何需要。 根据另外的实施例，当包括扩展存储器时，可以实现提高的操作效率以增强多组存储器之间的并发性。 扩展存储器的可寻址位置可以被映射到可用系统地址空间的底部，并且任何先前的基本系统存储器的寻址位置移动到扩展存储器空间之上。

公开(公告)号：US5642136A

公开(公告)日：1997-06-24

申请号：US661404

申请日：1996-06-07

Applicant: Rajeev Jayavant ,  William Desi Rhoden

Inventor： Rajeev Jayavant ,  William Desi Rhoden

IPC: G09G5/24 ,  G09G5/36 ,  G09G5/39

CPC classification number: G09G5/24 ,  G09G5/363

Abstract: In a text mode of a display controller, for each character of the text, a plurality of multiple-byte words are stored in a memory buffer. Each multiple-byte word contains an ASCII character code for the character, font attribute information for the character and at least one font line for the character. For each character font line to be displayed on the monitor, a multiple byte word is read. The attribute information and a first character font line are extracted from the multiple byte word. The display controller then constructs a character scan line for the character based on the attribute information and the first character font line. The character scan line may then be displaying on the monitor.

Abstract translation: 在显示控制器的文本模式中，对于文本的每个字符，多个多字节字被存储在存储器缓冲器中。 每个多字节字包含字符的ASCII字符代码，字符的字体属性信息和字符的至少一个字体行。 对于要在监视器上显示的每个字符字体行，读取多字节字。 从多字节字提取属性信息和第一字符字体行。 然后，显示控制器基于属性信息和第一字符字体行构建字符的字符扫描线。 然后，字符扫描线可以在监视器上显示。

公开(公告)号：US07256792B1

公开(公告)日：2007-08-14

申请号：US11493153

申请日：2006-07-26

Applicant: Walter E. Donovan ,  Rajeev Jayavant

Inventor： Walter E. Donovan ,  Rajeev Jayavant

IPC: G09G5/00 ,  G09T15/60 ,  G06T17/00 ,  G06K9/40

CPC classification number: G06T15/04

Abstract: An apparatus and method for using non-power of two texture maps is described. Normalized texture map coordinates such as s and t are converted from a floating point format to a fixed point format and wrapping operations are performed to produce unnormalized texture map coordinates such as u and v corresponding to non-power of two texture maps.

Abstract translation: 描述了使用两个纹理贴图的非幂的装置和方法。 归一化纹理映射坐标如s和t从浮点格式转换为固定点格式，并执行包装操作，以产生非标准纹理贴图坐标，例如对应于两个纹理贴图的非幂的u和v。

公开(公告)号：US06591347B2

公开(公告)日：2003-07-08

申请号：US09169312

申请日：1998-10-09

Applicant: Brett A. Tischler ,  Rajeev Jayavant

Inventor： Brett A. Tischler ,  Rajeev Jayavant

IPC: G06F1208

CPC classification number: G06F12/126 ,  G06F12/121 ,  G06F2212/6042

Abstract: A dynamically configurable replacement technique in a unified or shared cache reduces domination by a particular functional unit or an application such as unified instruction/data caching by limiting the eviction ability to selected cache regions based on over utilization of the cache by a particular functional unit or application. A specific application includes a highly integrated multimedia processor employing a tightly coupled shared cache between central processing and graphics units wherein the eviction ability of the graphics unit is limited to selected cache regions when the graphics unit over utilizes the cache. Dynamic configurability can take the form of a programmable register that enables either one of a plurality of replacement modes based on captured statistics such as measurement of cache misses by a particular functional unit or application.

Abstract translation: 统一或共享的高速缓存中的动态配置替换技术可以减少特定功能单元或诸如统一指令/数据高速缓存之类的应用程序的控制，这是通过限制特定功能单元对高速缓存的过度使用来限制所选高速缓存区域的逐出能力， 应用。 具体应用包括在中央处理和图形单元之间使用紧密耦合的共享高速缓存的高度集成的多媒体处理器，其中当图形单元过度使用高速缓存时，图形单元的驱逐能力被限制到所选择的高速缓存区域。 动态可配置性可以采用可编程寄存器的形式，其基于捕获的统计信息（诸如由特定功能单元或应用程序测量高速缓存未命中）启用多个替换模式中的一个。