公开(公告)号：US08271994B2

公开(公告)日：2012-09-18

申请号：US11353288

申请日：2006-02-11

申请人： Hiroshi Inoue ,  Moriyoshi Ohara ,  Takao Moriyama ,  Yukihiko Sohda ,  Hideaki Komatsu

发明人： Hiroshi Inoue ,  Moriyoshi Ohara ,  Takao Moriyama ,  Yukihiko Sohda ,  Hideaki Komatsu

IPC分类号： G06F9/46

CPC分类号： G06F9/462

摘要： Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

公开(公告)号：US20070192767A1

公开(公告)日：2007-08-16

申请号：US11353288

申请日：2006-02-11

申请人： Hiroshi Inoue ,  Moriyoshi Ohara ,  Takao Moriyama ,  Yukihiko Sohda ,  Hideaki Komatsu

发明人： Hiroshi Inoue ,  Moriyoshi Ohara ,  Takao Moriyama ,  Yukihiko Sohda ,  Hideaki Komatsu

IPC分类号： G06F9/46

CPC分类号： G06F9/462

摘要： Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

摘要翻译： 处理器上下文切换期间的数据传输减少，特别是在分时微任务编程模型方面。 在将具有本地存储器的处理器从第一处理切换到第二处理之前，确定不需要传送到系统存储器以适当地保存与第一处理相关联的数据的本地存储器的一部分。 然后，处理器的上下文从第一处理切换到第二处理，包括将与第一处理相关联的所有本地存储器传送到系统存储器 - 除了被确定为不是的本地存储器的部分之外 需要保存到系统存储器以适当地保存与第一进程相关联的数据。 因此，将上下文从第一处理切换到第二处理导致从本地存储器传送到系统存储器的数据的减少。

公开(公告)号：US20080270772A1

公开(公告)日：2008-10-30

申请号：US12172253

申请日：2008-07-13

申请人： Hiroshi Inoue ,  Moriyoshi Ohara ,  Takao Moriyama ,  Yukihiko Sohda ,  Hideaki Komatsu

发明人： Hiroshi Inoue ,  Moriyoshi Ohara ,  Takao Moriyama ,  Yukihiko Sohda ,  Hideaki Komatsu

IPC分类号： G06F9/312

CPC分类号： G06F9/462

摘要： Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

摘要翻译： 处理器上下文切换期间的数据传输减少，特别是在分时微任务编程模型方面。 在将具有本地存储器的处理器从第一处理切换到第二处理之前，确定不需要传送到系统存储器以适当地保存与第一处理相关联的数据的本地存储器的一部分。 然后，处理器的上下文从第一处理切换到第二处理，包括将与第一处理相关联的所有本地存储器传送到系统存储器 - 除了被确定为不是的本地存储器的部分之外 需要保存到系统存储器以适当地保存与第一进程相关联的数据。 因此，将上下文从第一处理切换到第二处理导致从本地存储器传送到系统存储器的数据的减少。

公开(公告)号：US20120297398A1

公开(公告)日：2012-11-22

申请号：US13563713

申请日：2012-07-31

申请人： Hiroshi Inoue ,  Moriyoshi Ohara ,  Takao Moriyama ,  Yukihiko Sohda ,  Hideaki Komatsu

发明人： Hiroshi Inoue ,  Moriyoshi Ohara ,  Takao Moriyama ,  Yukihiko Sohda ,  Hideaki Komatsu

IPC分类号： G06F9/46

CPC分类号： G06F9/462

摘要： Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

摘要翻译： 处理器上下文切换期间的数据传输减少，特别是在分时微任务编程模型方面。 在将具有本地存储器的处理器从第一处理切换到第二处理之前，确定不需要传送到系统存储器以适当地保存与第一处理相关联的数据的本地存储器的一部分。 然后，处理器的上下文从第一处理切换到第二处理，包括将与第一处理相关联的所有本地存储器传送到系统存储器 - 除了被确定为不是的本地存储器的部分之外 需要保存到系统存储器以适当地保存与第一进程相关联的数据。 因此，将上下文从第一处理切换到第二处理导致从本地存储器传送到系统存储器的数据的减少。

公开(公告)号：US20070038987A1

公开(公告)日：2007-02-15

申请号：US11463496

申请日：2006-08-09

申请人： Moriyoshi Ohara ,  Yukihiko Sohda ,  Hiroshi Inoue ,  Takao Moriyama ,  Hideaki Komatsu

发明人： Moriyoshi Ohara ,  Yukihiko Sohda ,  Hiroshi Inoue ,  Takao Moriyama ,  Hideaki Komatsu

IPC分类号： G06F9/45

CPC分类号： G06F8/45

摘要： Provided is a complier which optimizes parallel processing. The complier records the number of execution cores, which is the number of processor cores that execute a target program. First, the compiler detects a dominant path, which is a candidate of an execution path to be consecutively executed by a single processor core, from a target program. Subsequently, the compiler selects dominant paths with the number not larger than the number of execution cores, and generates clusters of tasks to be executed by a multi-core processor in parallel or consecutively. After that, the compiler computes an execution time for which each of the generated clusters is executed by the processor cores with the number equal to one or each of a plurality natural numbers selected from the natural numbers not larger than the number of execution cores. Then, the compiler selects the number of processor cores to be assigned for execution of each of the clusters based on the computed execution time.

摘要翻译： 提供了优化并行处理的编译器。 编译器记录执行核心数量，即执行目标程序的处理器核心数。 首先，编译器从目标程序检测作为由单个处理器核心连续执行的执行路径的候选者的主路径。 随后，编译器选择不大于执行核心数量的主导路径，并且并行或连续地生成由多核处理器执行的任务集群。 之后，编译器计算执行时间，其中每个生成的集群由处理器核执行，数量等于从不大于执行核心数的自然数中选择的多个自然数中的一个或每个。 然后，编译器基于计算出的执行时间选择要分配用于每个簇的执行的处理器核心的数量。

公开(公告)号：US08769547B2

公开(公告)日：2014-07-01

申请号：US13563713

申请日：2012-07-31

申请人： Hiroshi Inoue ,  Moriyoshi Ohara ,  Takao Moriyama ,  Yukihiko Sohda ,  Hideaki Komatsu

发明人： Hiroshi Inoue ,  Moriyoshi Ohara ,  Takao Moriyama ,  Yukihiko Sohda ,  Hideaki Komatsu

IPC分类号： G06F9/46

CPC分类号： G06F9/462

摘要： Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

摘要翻译： 处理器上下文切换期间的数据传输减少，特别是在分时微任务编程模型方面。 在将具有本地存储器的处理器从第一处理切换到第二处理之前，确定不需要传送到系统存储器以适当地保存与第一处理相关联的数据的本地存储器的一部分。 然后，处理器的上下文从第一处理切换到第二处理，包括将与第一处理相关联的所有本地存储器传送到系统存储器 - 除了被确定为不是的本地存储器的部分之外 需要保存到系统存储器以适当地保存与第一进程相关联的数据。 因此，将上下文从第一处理切换到第二处理导致从本地存储器传送到系统存储器的数据的减少。

公开(公告)号：US08266627B2

公开(公告)日：2012-09-11

申请号：US12172253

申请日：2008-07-13

申请人： Hiroshi Inoue ,  Moriyoshi Ohara ,  Takao Moriyama ,  Yukihiko Sohda ,  Hideaki Komatsu

发明人： Hiroshi Inoue ,  Moriyoshi Ohara ,  Takao Moriyama ,  Yukihiko Sohda ,  Hideaki Komatsu

IPC分类号： G06F9/46

CPC分类号： G06F9/462

摘要： Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

公开(公告)号：US07503039B2

公开(公告)日：2009-03-10

申请号：US11463496

申请日：2006-08-09

申请人： Hiroshi Inoue ,  Hideaki Komatsu ,  Takao Moriyama ,  Moriyoshi Ohara ,  Yukihiko Sohda

发明人： Hiroshi Inoue ,  Hideaki Komatsu ,  Takao Moriyama ,  Moriyoshi Ohara ,  Yukihiko Sohda

IPC分类号： G06F9/45 ,  G06F9/46

CPC分类号： G06F8/45

摘要： Provided is a complier which optimizes parallel processing. The complier records the number of execution cores, which is the number of processor cores that execute a target program. First, the compiler detects a dominant path, which is a candidate of an execution path to be consecutively executed by a single processor core, from a target program. Subsequently, the compiler selects dominant paths with the number not larger than the number of execution cores, and generates clusters of tasks to be executed by a multi-core processor in parallel or consecutively. After that, the compiler computes an execution time for which each of the generated clusters is executed by the processor cores with the number equal to one or each of a plurality natural numbers selected from the natural numbers not larger than the number of execution cores. Then, the compiler selects the number of processor cores to be assigned for execution of each of the clusters based on the computed execution time.

摘要翻译： 提供了优化并行处理的编译器。 编译器记录执行核心数量，即执行目标程序的处理器核心数。 首先，编译器从目标程序检测作为由单个处理器核心连续执行的执行路径的候选者的主路径。 随后，编译器选择不大于执行核心数量的主导路径，并且并行或连续地生成由多核处理器执行的任务集群。 之后，编译器计算执行时间，其中每个生成的集群由处理器核执行，数量等于从不大于执行核心数的自然数中选择的多个自然数中的一个或每个。 然后，编译器基于计算出的执行时间选择要分配用于每个簇的执行的处理器核心的数量。

公开(公告)号：US08677484B2

公开(公告)日：2014-03-18

申请号：US13419554

申请日：2012-03-14

申请人： Seiji Munetoh ,  Akira Ohkado ,  Yukihiko Sohda ,  Masami Tada

发明人： Seiji Munetoh ,  Akira Ohkado ,  Yukihiko Sohda ,  Masami Tada

IPC分类号： G06F11/00 ,  G06F12/14 ,  G06F12/16 ,  G08B23/00

CPC分类号： G06F21/554 ,  G06F9/45533 ,  G06F21/74 ,  G06F2221/2127 ,  H04L63/1491

摘要： A system includes a detection unit configured to detect unauthorized access to one or more information processing apparatuses that are virtually implemented by virtual machines executed by a computer; an authorized network configured to transfer authorized access to the one or more information processing apparatuses from an external network; a honeypot network configured to transfer unauthorized access to the information processing apparatuses from the external network; and a control unit configured to connect the information processing apparatuses for which no unauthorized access has been detected to the authorized network, and connect the information processing apparatuses for which unauthorized access has been detected to the honeypot network; wherein the control unit shifts, in response to detecting unauthorized access by the detection unit, the corresponding information processing apparatus into a decoy mode in which the detected unauthorized access is disconnected from a normal operation.

摘要翻译： 一种系统，包括：检测单元，被配置为检测对由计算机执行的虚拟机虚拟实现的一个或多个信息处理设备的未授权访问; 授权网络，被配置为从外部网络传送对所述一个或多个信息处理设备的授权访问; 蜜罐网络，被配置为从外部网络传送对信息处理设备的未经授权的访问; 以及控制单元，被配置为将没有未经授权的访问的信息处理设备连接到授权网络，并且将已经检测到未经授权的访问的信息处理设备连接到蜜罐网络; 其中所述控制单元响应于检测到所述检测单元的未经授权的访问而将所述对应的信息处理设备移动到所述检测到的未授权访问与正常操作断开的诱饵模式。

公开(公告)号：US08683589B2

公开(公告)日：2014-03-25

申请号：US13560471

申请日：2012-07-27

申请人： Seiji Munetoh ,  Akira Ohkado ,  Yukihiko Sohda ,  Masami Tada

发明人： Seiji Munetoh ,  Akira Ohkado ,  Yukihiko Sohda ,  Masami Tada

IPC分类号： G06F11/00 ,  G06F12/14 ,  G06F12/16 ,  G08B23/00

CPC分类号： G06F21/554 ,  G06F9/45533 ,  G06F21/74 ,  G06F2221/2127 ,  H04L63/1491

摘要： A system includes a detection unit configured to detect unauthorized access to one or more information processing apparatuses that are virtually implemented by virtual machines executed by a computer; an authorized network configured to transfer authorized access to the one or more information processing apparatuses from an external network; a honeypot network configured to transfer unauthorized access to the information processing apparatuses from the external network; and a control unit configured to connect the information processing apparatuses for which no unauthorized access has been detected to the authorized network, and connect the information processing apparatuses for which unauthorized access has been detected to the honeypot network; wherein the control unit shifts, in response to detecting unauthorized access by the detection unit, the corresponding information processing apparatus into a decoy mode in which the detected unauthorized access is disconnected from a normal operation.