公开(公告)号：US08654573B2

公开(公告)日：2014-02-18

申请号：US13743794

申请日：2013-01-17

Applicant: Mosaid Technologies Incorporated

Inventor： Peter B. Gillingham ,  Bruce Millar

IPC: G11C11/00

CPC classification number: G11C5/06 ,  G06F1/12 ,  G06F13/1689 ,  G06F13/4234 ,  G06F13/4243 ,  G11C8/18 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device.

Abstract translation: 一种包括缓冲器和多个同步存储器件的存储器模块。 存储器模块还包括双向总线，并且每个同步存储器件具有双向数据终端。 缓冲器被配置为重新生成在总线上接收的信号以供同步存储器件接收，并且重新产生从任何一个同步存储器装置接收的信号，以便由总线接收。 存储器模块还可以包括命令行和用于经由命令缓冲器向同步存储器件提供命令和时钟信号的时钟线。 存储器模块的组合数据总线宽度可以大于同步存储器件中任何一个的数据总线宽度，并且由存储器模块提供的总地址空间可能大于任何单个同步存储器件的数据空间。