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12 条记录 (耗时 0.033 秒)

    SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP
    8.
    发明申请
    SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP 失效
    VLSI芯片的关闭时序关闭的系统和方法

    公开(公告)号：US20080209376A1

    公开(公告)日：2008-08-28

    申请号：US11680110

    申请日：2007-02-28

    申请人： Michael A. Kazda ,  Pooja M. Kotecha ,  Adam P. Matheny ,  Lakshmi Reddy ,  Louise H. Trevillyan ,  Paul G. Villarrubia

    发明人： Michael A. Kazda ,  Pooja M. Kotecha ,  Adam P. Matheny ,  Lakshmi Reddy ,  Louise H. Trevillyan ,  Paul G. Villarrubia

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/84

    摘要： A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

    摘要翻译： 一种用于以紧密耦合的递增方式对细节路由网表执行定时优化的方法，其以最小的扰动对放置，路由和断言的寄生信息进行并入，并入统计变异信息，公共路径悲观度降低和电容耦合信息。 该方法校正了VLSI电路芯片的放置和路由设计中的违规，其中设计由描述设计的逻辑和物理特性的网表以及对应的时序图表示，该方法包括以下步骤：识别 设计; 通过逐步改变设计的逻辑和物理特征，迭代地消除违规行为，仅在设计中纳入合法的布局和路线; 并应用增量时间来评估变革，并更新现有的时间图，以反映由法定刊登位置和路线组成的变更。

    System and method for sign-off timing closure of a VLSI chip
    9.
    发明授权
    System and method for sign-off timing closure of a VLSI chip 失效
    用于签发VLSI芯片的定时关闭的系统和方法

    公开(公告)号：US07581201B2

    公开(公告)日：2009-08-25

    申请号：US11680110

    申请日：2007-02-28

    申请人： Michael A. Kazda ,  Pooja M. Kotecha ,  Adam P. Matheny ,  Lakshmi Reddy ,  Louise H. Trevillyan ,  Paul G. Villarrubia

    发明人： Michael A. Kazda ,  Pooja M. Kotecha ,  Adam P. Matheny ,  Lakshmi Reddy ,  Louise H. Trevillyan ,  Paul G. Villarrubia

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/84

    摘要： A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

    摘要翻译： 一种用于以紧密耦合的递增方式对细节路由网表执行定时优化的方法，其以最小的扰动对放置，路由和断言的寄生信息进行并入，并入统计变异信息，公共路径悲观度降低和电容耦合信息。 该方法校正了VLSI电路芯片的放置和路由设计中的违规，其中设计由描述设计的逻辑和物理特性的网表以及对应的时序图表示，该方法包括以下步骤：识别 设计; 通过逐步改变设计的逻辑和物理特征，迭代地消除违规行为，仅在设计中纳入合法的布局和路线; 并应用增量时间来评估变革，并更新现有的时间图，以反映由法定刊登位置和路线组成的变更。

    REDUCING REPEATER POWER
    10.
    发明申请
    REDUCING REPEATER POWER 有权
    降低重复功率

    公开(公告)号：US20130275110A1

    公开(公告)日：2013-10-17

    申请号：US13447751

    申请日：2012-04-16

    申请人： Paul D. Kartschoke ,  Adam P. Matheny ,  Jose L. Neves

    发明人： Paul D. Kartschoke ,  Adam P. Matheny ,  Jose L. Neves

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/5036

    摘要： A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.

    摘要翻译： 提供了用于减少中继器功率和串扰的方法，系统和计算机可读介质。 该方法包括生成包括连接在至少一个源和至少一个宿之间的多个原始中继器的电路的模型，对多个原始中继器执行功率优化分析以将多个原始中继器改变为低功率中继器 基于预定的优化参数，对包括低功率中继器的电路的模型执行串扰分析，以确定是否存在串扰定时违反，以及当至少一个低功率中继器改变为较高功率中继器时 确定存在串扰冲突，并且当确定不存在串扰冲突时，将低功率中继器留在电路模型中。