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    Write buffer for improved DRAM write access patterns
    1.
    发明授权
    Write buffer for improved DRAM write access patterns 失效
    写缓冲区，用于改进DRAM写访问模式

    公开(公告)号：US08495286B2

    公开(公告)日：2013-07-23

    申请号：US12962774

    申请日：2010-12-08

    申请人： Cagri Balkesen ,  Markus Buehler ,  Rainer Dorsch ,  Guenther Hutzl ,  Michael W. Kaufmann ,  Daniel Pfefferkorn ,  David Rohr ,  Stefanie Scherzinger ,  Thomas Schwarz

    发明人： Cagri Balkesen ,  Markus Buehler ,  Rainer Dorsch ,  Guenther Hutzl ,  Michael W. Kaufmann ,  Daniel Pfefferkorn ,  David Rohr ,  Stefanie Scherzinger ,  Thomas Schwarz

    IPC分类号： G06F12/00 ,  G06F3/00

    CPC分类号： G06F12/0804 ,  G06F12/0215 ,  G06F12/0897 ,  Y02D10/13

    摘要： The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.

    摘要翻译： 本发明涉及用于操作DRAM主存储器的方法和相应的系统。 为多页提供一条缓冲线。 当向缓冲器写入数据时，根据其目的主存储器地址确定数据被写入哪个缓冲行。 存储由较低内存地址和数据组成的元组。 输入缓冲线的数据将按页进行排序，以防线路被刷新到主存储器。 对缓冲区条目进行排序会导致更少的页面打开和关闭，因为数据由存储器地址重新排列，因此以逻辑顺序排列。 通过对多个页面使用一行，只需要一个共同的组相关高速缓存的一部分存储器，从而显着地减少了开销。

    Glitch power reduction
    2.
    发明授权
    Glitch power reduction 失效
    毛刺功率降低

    公开(公告)号：US08407654B2

    公开(公告)日：2013-03-26

    申请号：US13365972

    申请日：2012-02-03

    申请人： Thomas Buechner ,  Markus Buehler ,  Markus Olbrich ,  Philipp Panitz ,  Lei Wang

    发明人： Thomas Buechner ,  Markus Buehler ,  Markus Olbrich ,  Philipp Panitz ,  Lei Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/78

    摘要： A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value. For each selected gate, performing operations comprising: testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration with minimum upper bound for power consumption; and modifying the gate-level design representation according to the selected gate configuration.

    摘要翻译： 一种方法包括降低电子电路的功耗，其中电子电路包括至少一个具有至少一个具有单个输出网的门的逻辑锥，其中至少一个门的表示是来自标准单元库的元件的实例。 降低功耗包括通过计算每个门的转换度量和功率度量来确定动态功耗的上限。 降低功耗包括选择具有大于预定阈值的功耗上限的门。 对于每个所选择的门，执行操作包括：通过针对所述多个配置中的每一个计算相应的功耗上限来测试来自所选择的门的标准单元库的多个配置; 选择门极配置，最小上限为功耗; 以及根据选择的门配置修改门级设计表示。

    Routing of wires of an electronic circuit
    4.
    发明授权
    Routing of wires of an electronic circuit 有权
    电路电路布线

    公开(公告)号：US08015527B2

    公开(公告)日：2011-09-06

    申请号：US12166012

    申请日：2008-07-01

    申请人： Markus Buehler ,  Juergen Koehl ,  Markus Olbrich ,  Philipp Panitz

    发明人： Markus Buehler ,  Juergen Koehl ,  Markus Olbrich ,  Philipp Panitz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： The invention relates to a delay calculation method for wiring nets of an electronic circuit, wherein a net within an electronic circuit comprises a driver pin and a receiving pin being coupled by at least one loop, the loop comprising a first branching path and a second branching path electrically parallel to the first branching path, wherein at least a first and a second branching point connect the branching paths. The method comprises the steps of disconnecting each branching path once at a time at a specific point in said the at least one loop which connects a driver to at least one specific receiving pin; calculating a delay value of a signal connection between the driver pin and each of the receiving pin for each of the disconnected branching paths of each loop; storing maximum and/or minimum calculated delay values; and applying at least one of the delay values for static timing analysis of the electronic circuit.

    摘要翻译： 本发明涉及一种用于电子电路布线网的延迟计算方法，其中电子电路内的网包括一个驱动器引脚和一个由至少一个环耦合的接收引脚，该环包括第一分支路径和第二分支 所述路径电平行于所述第一分支路径，其中至少第一和第二分支点连接所述分支路径。 该方法包括以下步骤：在连接驱动器至少一个特定接收引脚的所述至少一个回路中的特定点处一次断开每个分支路径; 计算每个循环的每个断开的分支路径的驱动器引脚和每个接收引脚之间的信号连接的延迟值; 存储最大和/或最小计算的延迟值; 以及对电子电路的静态时序分析应用至少一个延迟值。

    Test yield estimate for semiconductor products created from a library
    5.
    发明授权
    Test yield estimate for semiconductor products created from a library 有权
    从图书馆创建的半导体产品的测试产量估算

    公开(公告)号：US08010916B2

    公开(公告)日：2011-08-30

    申请号：US12062586

    申请日：2008-04-04

    申请人： Jeanne Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl

    发明人： Jeanne Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.

    摘要翻译： 公开了一种在设计布局之前预测半导体产品的测试产量的方法。 这是通过对用于形成特定产品的单个库元素应用关键区域分析，并通过估计组合这些库元素的测试产出影响来实现的。 例如，该方法考虑了库元素对库元素短路的灵敏度的测试产量影响以及对接线故障的灵敏度的测试产量影响。 所公开的方法进一步允许模具尺寸增长与使用具有较高测试成品率的库元件进行交易，以便提供最佳设计解决方案。 因此，该方法可用于修改库元素选择以优化测试产量。 最后，该方法在关键设计检查点进一步重复，以重新验证产品被引用给客户时的初始测试收益（和成本）假设。 因此，该方法通过设计从初始尺寸提高了测试产量估算的准确度，并进一步允许修改设计以提高测试产量。

    Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same
    6.
    发明授权
    Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same 有权
    冗余微环结构用于集成电路物理设计过程及其形成方法

    公开(公告)号：US07960836B2

    公开(公告)日：2011-06-14

    申请号：US12045374

    申请日：2008-03-10

    申请人： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

    IPC分类号： H01L23/52

    CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and Fourth wires form a path between the first and second wires redundant to the first via.

    摘要翻译： 一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和与第二线的第一距离的第四线 第二层线路。 第一通孔在第二导线的第一位置连接第一和第二导线。 第二通孔在第一位置处连接第二和第三导线，第二通孔基本上与第一通孔轴向对准。 第三通过在第四线的第二位置连接第三和第四导线。 第四通孔在第二位置处连接第一和第四导线，第四通孔基本上与第三通孔轴向对准。 第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

    TEST YIELD ESTIMATE FOR SEMICONDUCTOR PRODUCTS CREATED FROM A LIBRARY
    9.
    发明申请
    TEST YIELD ESTIMATE FOR SEMICONDUCTOR PRODUCTS CREATED FROM A LIBRARY 有权
    从图书馆创建的半导体产品的测试估计

    公开(公告)号：US20080189664A1

    公开(公告)日：2008-08-07

    申请号：US12062586

    申请日：2008-04-04

    申请人： Jeanne Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl

    发明人： Jeanne Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield impact of combining these library elements. For example, the method considers the test yield impact of sensitivity to library element to library element shorts and the test yield impact of sensitivity to wiring faults. The disclosed method further allows die size growth to be traded off against the use of library elements with higher test yield in order to provide an optimal design solution. Thus, the method may be used to modify library element selection so as to optimize test yield. Lastly, the method further repeats itself at key design checkpoints to revalidate initial test yield (and cost) assumptions made when the product was quoted to a customer. Thus, the method provides increased accuracy of test yield estimate from initial sizing through design and further allows designs to be modified to improve test yield.

    摘要翻译： 公开了一种在设计布局之前预测半导体产品的测试产量的方法。 这是通过对用于形成特定产品的单个库元素应用关键区域分析，并通过估计组合这些库元素的测试产出影响来实现的。 例如，该方法考虑了库元素对库元素短路的灵敏度的测试产量影响以及对接线故障的灵敏度的测试产量影响。 所公开的方法进一步允许模具尺寸增长与使用具有较高测试成品率的库元件进行交易，以便提供最佳设计解决方案。 因此，该方法可用于修改库元素选择以优化测试产量。 最后，该方法在关键设计检查点进一步重复，以重新验证产品被引用给客户时的初始测试收益（和成本）假设。 因此，该方法通过设计从初始尺寸提高了测试产量估算的准确度，并进一步允许修改设计以提高测试产量。

    REDUNDANT MICRO-LOOP STRUCTURE FOR USE IN AN INTERGRATED CIRCUIT PHYSICAL DESIGN PROCESS AND METHOD OF FORMING THE SAME
    10.
    发明申请
    REDUNDANT MICRO-LOOP STRUCTURE FOR USE IN AN INTERGRATED CIRCUIT PHYSICAL DESIGN PROCESS AND METHOD OF FORMING THE SAME 有权
    用于集成电路的冗余微环结构物理设计过程及其形成方法

    公开(公告)号：US20080150149A1

    公开(公告)日：2008-06-26

    申请号：US12045374

    申请日：2008-03-10

    申请人： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

    IPC分类号： H01L23/52 ,  G06F17/50

    CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and Fourth wires form a path between the first and second wires redundant to the first via.

    摘要翻译： 一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和与第二线的第一距离的第四线 第二层线路。 第一通孔在第二导线的第一位置连接第一和第二导线。 第二通孔在第一位置处连接第二和第三导线，第二通孔基本上与第一通孔轴向对准。 第三通过在第四线的第二位置连接第三和第四导线。 第四通孔在第二位置处连接第一和第四导线，第四通孔基本上与第三通孔轴向对准。 第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。