公开(公告)号：US20130326447A1

公开(公告)日：2013-12-05

申请号：US13484480

申请日：2012-05-31

申请人： Mu-Jen HUANG ,  Yu-Sian JIANG ,  Yi-Ting LIN ,  Hsien-Yu TSENG ,  Heng Kai LIU ,  Chien-Wen CHEN ,  Chauchin SU

发明人： Mu-Jen HUANG ,  Yu-Sian JIANG ,  Yi-Ting LIN ,  Hsien-Yu TSENG ,  Heng Kai LIU ,  Chien-Wen CHEN ,  Chauchin SU

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/82

摘要： A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.

摘要翻译： 一种系统包括电子设计自动化（EDA）工具，用于产生集成电路（IC）的示意性设计，从原理图设计生成布局，编辑布局以及验证原理图设计和布局。 提供了至少一个非暂时的计算机可读存储介质，用于存储表示示意图设计和布局的数据，该布局具有连接IC设计的至少两个有源层设备的路由路径网络。 提供了一种RC工具，用于在验证原理图设计和布局之前计算网络路由路径的估计寄生电容，并将与估计的寄生电容对应的电容插入到表示IC原理图设计的数据中。 用于基于至少两个有源层器件和估计的寄生电容来模拟网络的性能的第一器件级仿真工具。