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公开(公告)号：US10895980B2
公开(公告)日：2021-01-19
申请号：US16677608
申请日：2019-11-07
申请人： Yu-Sian Jiang
发明人： Yu-Sian Jiang
IPC分类号： G06F3/041 , G06F3/0488 , G06K9/00 , G06F21/32 , G06K9/20 , H04N13/368
摘要： A method of operating an electronic system for is provided. The method includes the following actions. A plurality of images are captured by an image capturing unit. An object is detected by a sensor unit within a sensing region. When the object is detected within the sensing region of the sensor unit, a palm feature is recognized by a processing unit from the captured images. An application is stimulated in response to the palm feature.
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公开(公告)号：US20200221000A1
公开(公告)日：2020-07-09
申请号：US16737897
申请日：2020-01-08
申请人： Yu-Sian Jiang , Mu-Jen Huang
发明人： Yu-Sian Jiang , Mu-Jen Huang
摘要： A camera system is provided. The camera system includes an image sensor, at least one light source, and a processing unit. The image sensor is configured to capture a plurality of images. The processing unit is configured to perform the following instructions. A plurality of reflection values on at least one subject in the captured images is acquired. A relationship between a luminance level of the light sources and a reflection level on the at least one subject is obtained. A luminance configuration is determined according to the relationship between the luminance level of the light sources and the reflection level on the at least one subject. A luminous power of at least one of the light sources is adjusted according to the luminance configuration.
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公开(公告)号：US20200150916A1
公开(公告)日：2020-05-14
申请号：US16679150
申请日：2019-11-09
申请人： Yu-Sian Jiang
发明人： Yu-Sian Jiang
摘要： A display system is provided. The display system includes a first display panel, a second display panel, and a processing unit. The first display panel is configured to display a first content. The second display panel is configured to display a second content, where a gap is between a frame of the first display panel and a frame of the second display panel, and the first content and the second content share a same 3D world coordinate. The processing unit is configured to establish a scene, where the scene is jointly displayed by the first content rendered in the first display panel and the second content rendered in the second display panel. The scene includes a third content that is not shown on the first display panel or the second display panel.
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公开(公告)号：US08745552B2
公开(公告)日：2014-06-03
申请号：US13484488
申请日：2012-05-31
申请人： Hsien-Yu Tseng , Shih-Kai Lin , Chin-Shen Lin , Yu-Sian Jiang , Heng-Kai Liu , Mu-Jen Huang , Chien-Wen Chen
发明人： Hsien-Yu Tseng , Shih-Kai Lin , Chin-Shen Lin , Yu-Sian Jiang , Heng-Kai Liu , Mu-Jen Huang , Chien-Wen Chen
IPC分类号： G06F17/50
CPC分类号： H01L23/528 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L21/76816 , H01L23/53228 , H01L27/0207
摘要： A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.
摘要翻译： 一种方法包括：访问表示集成电路（IC）的层的布局的数据，所述集成电路的层包括多个多边形，所述多边形限定电路图案，以划分数个（N）个光掩模，用于多个图案化半导体衬底的单层; 其中N大于1。 对于布局中的每个N个平行多边形组合，彼此比用用于单一光掩模进行图案化的最小间隔更靠近，至少N-1个针脚被插入到该组内的每个多边形中以将每个多边形分成至少N个部分，例如 不同多边形的相邻部分被分配给彼此不同的光掩模。 表示将每个组中的每个部分分配给相应光掩模的数据被存储在非瞬时的计算机可读存储介质中，该介质可访问以用于制造N个光掩模的过程。
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公开(公告)号：US20130320555A1
公开(公告)日：2013-12-05
申请号：US13484488
申请日：2012-05-31
申请人： Hsien YU-TSENG , Shih-Kai LIN , Chin-Shen LIN , Yu-Sian JIANG , Heng-Kai LIU , Mu-Jen HUANG , Chien-Wen CHEN
发明人： Hsien YU-TSENG , Shih-Kai LIN , Chin-Shen LIN , Yu-Sian JIANG , Heng-Kai LIU , Mu-Jen HUANG , Chien-Wen CHEN
CPC分类号： H01L23/528 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L21/76816 , H01L23/53228 , H01L27/0207
摘要： A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.
摘要翻译： 一种方法包括：访问表示集成电路（IC）的层的布局的数据，所述集成电路的层包括多个多边形，所述多边形限定电路图案，以划分数个（N）个光掩模，用于多个图案化半导体衬底的单层; 其中N大于1。 对于布局中的每个N个平行多边形组合，彼此比用用于单一光掩模进行图案化的最小间隔更靠近，在该组内的每个多边形中插入至少N-1个针脚，以将每个多边形分成至少N个部分，例如 不同多边形的相邻部分被分配给彼此不同的光掩模。 表示将每个组中的每个部分分配给相应光掩模的数据被存储在非瞬时的计算机可读存储介质中，该介质可访问以用于制造N个光掩模的过程。
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公开(公告)号：US20120304146A1
公开(公告)日：2012-11-29
申请号：US13115752
申请日：2011-05-25
申请人： Yu-Sian Jiang , Ya-Li Tai , Mu-Jen Huang , Chien-Wen Chen , Chauchin Su
发明人： Yu-Sian Jiang , Ya-Li Tai , Mu-Jen Huang , Chien-Wen Chen , Chauchin Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A design system includes a layout module and a user interface. The layout module includes a computing unit, which is configured to extract layout parameters of an integrated circuit device in a circuit during a layout stage of the circuit, and calculate circuit parameters of the device using the layout parameters. The user interface is configured to display the circuit parameters of the device in response to a user selection of the device.
摘要翻译： 设计系统包括布局模块和用户界面。 布局模块包括计算单元，其被配置为在电路的布局阶段期间提取电路中的集成电路器件的布局参数，并且使用布局参数来计算器件的电路参数。 用户界面被配置为响应于用户对设备的选择来显示设备的电路参数。
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公开(公告)号：US20130326447A1
公开(公告)日：2013-12-05
申请号：US13484480
申请日：2012-05-31
申请人： Mu-Jen HUANG , Yu-Sian JIANG , Yi-Ting LIN , Hsien-Yu TSENG , Heng Kai LIU , Chien-Wen CHEN , Chauchin SU
发明人： Mu-Jen HUANG , Yu-Sian JIANG , Yi-Ting LIN , Hsien-Yu TSENG , Heng Kai LIU , Chien-Wen CHEN , Chauchin SU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/82
摘要： A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.
摘要翻译： 一种系统包括电子设计自动化（EDA）工具，用于产生集成电路（IC）的示意性设计，从原理图设计生成布局，编辑布局以及验证原理图设计和布局。 提供了至少一个非暂时的计算机可读存储介质，用于存储表示示意图设计和布局的数据，该布局具有连接IC设计的至少两个有源层设备的路由路径网络。 提供了一种RC工具，用于在验证原理图设计和布局之前计算网络路由路径的估计寄生电容，并将与估计的寄生电容对应的电容插入到表示IC原理图设计的数据中。 用于基于至少两个有源层器件和估计的寄生电容来模拟网络的性能的第一器件级仿真工具。
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公开(公告)号：US11272086B2
公开(公告)日：2022-03-08
申请号：US16737897
申请日：2020-01-08
申请人： Yu-Sian Jiang , Mu-Jen Huang
发明人： Yu-Sian Jiang , Mu-Jen Huang
摘要： A camera system is provided. The camera system includes an image sensor, at least one light source, and a processing unit. The image sensor is configured to capture a plurality of images. The processing unit is configured to perform the following instructions. A plurality of reflection values on at least one subject in the captured images is acquired. A relationship between a luminance level of the light sources and a reflection level on the at least one subject is obtained. A luminance configuration is determined according to the relationship between the luminance level of the light sources and the reflection level on the at least one subject. A luminous power of at least one of the light sources is adjusted according to the luminance configuration.
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公开(公告)号：US10896017B2
公开(公告)日：2021-01-19
申请号：US16679150
申请日：2019-11-09
申请人： Yu-Sian Jiang
发明人： Yu-Sian Jiang
摘要： A display system is provided. The display system includes a first display panel, a second display panel, and a processing unit. The first display panel is configured to display a first content. The second display panel is configured to display a second content, where a gap is between a frame of the first display panel and a frame of the second display panel, and the first content and the second content share a same 3D world coordinate. The processing unit is configured to establish a scene, where the scene is jointly displayed by the first content rendered in the first display panel and the second content rendered in the second display panel. The scene includes a third content that is not shown on the first display panel or the second display panel.
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公开(公告)号：US08806414B2
公开(公告)日：2014-08-12
申请号：US13484480
申请日：2012-05-31
申请人： Mu-Jen Huang , Yu-Sian Jiang , Yi-Ting Lin , Hsien-Yu Tseng , Heng Kai Liu , Chien-Wen Chen , Chauchin Su
发明人： Mu-Jen Huang , Yu-Sian Jiang , Yi-Ting Lin , Hsien-Yu Tseng , Heng Kai Liu , Chien-Wen Chen , Chauchin Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/82
摘要： A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.
摘要翻译： 一种系统包括电子设计自动化（EDA）工具，用于产生集成电路（IC）的示意性设计，从原理图设计生成布局，编辑布局以及验证原理图设计和布局。 提供了至少一个非暂时的计算机可读存储介质，用于存储表示示意图设计和布局的数据，该布局具有连接IC设计的至少两个有源层设备的路由路径网络。 提供了一种RC工具，用于在验证原理图设计和布局之前计算网络路由路径的估计寄生电容，并将与估计的寄生电容对应的电容插入到表示IC原理图设计的数据中。 用于基于至少两个有源层器件和估计的寄生电容来模拟网络的性能的第一器件级仿真工具。
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