公开(公告)号：US07113560B1

公开(公告)日：2006-09-26

申请号：US10253293

申请日：2002-09-24

申请人： Mu-Jen Huang ,  Linhsiang Wei ,  Fu-Shing Ju

发明人： Mu-Jen Huang ,  Linhsiang Wei ,  Fu-Shing Ju

IPC分类号： H04L7/00

CPC分类号： H04L7/0338

摘要： A method and circuit to produce an optimal sampling phase for recovery of a digital signal is achieved. A digital signal is over-sampled by sampling on each phase of a multiple phase clock to generate a sample value per phase. The multiple phase clock may be generated by a DLL. A voted value is determined per phase comprising a majority value of a set of consecutive sample values. Transition phases are sensed. A transition phase is defined as two consecutive voted phases comprising different values. The transition phases are compared to a stored phase state to determine a signal shift direction. The signal shift direction is filtered to generate a state update signal. The stored phase state is updated based on the state update signal. The stored phase state corresponds to an optimal sampling phase for recovery of the digital signal.

摘要翻译： 实现了用于产生用于恢复数字信号的最佳采样相位的方法和电路。 数字信号通过对多相时钟的每相进行采样而被过采样，以产生每相的采样值。 多相时钟可以由DLL生成。 每个阶段确定包括一组连续样本值的多数值的投票值。 检测过渡阶段。 过渡阶段被定义为包括不同值的两个连续投票阶段。 将过渡阶段与存储的相位状态进行比较以确定信号偏移方向。 信号移位方向被滤波以产生状态更新信号。 基于状态更新信号来更新存储的相位状态。 存储的相位状态对应于用于恢复数字信号的最佳采样相位。