公开(公告)号：US20230010467A1

公开(公告)日：2023-01-12

申请号：US17945462

申请日：2022-09-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yohei YAMAGUCHI ,  Yasuhiro MURASE ,  Stéphane BOUVIER

IPC: H01L27/01

Abstract: RC-network components that include a substrate and capacitor having a thin-film top electrode portion at a surface on one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion by an insulating layer, and a set of one or more bridging contacts passing through openings in the insulating layer. The bridging contacts electrically interconnect the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The openings are elongated thereby reducing temperature concentration at their periphery. Correspondingly, the bridging contacts have an elongated cross-sectional shape.

公开(公告)号：US20230017133A1

公开(公告)日：2023-01-19

申请号：US17935296

申请日：2022-09-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yohei YAMAGUCHI ,  Yasuhiro MURASE ,  Stéphane BOUVIER

IPC: H01L27/06 ,  H01L27/01 ,  H01L29/94

Abstract: RC-network components that include a substrate having a capacitor with a thin-film top electrode portion at a surface at one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance in series with the capacitor is controlled by providing a contact plate, spaced from the top electrode portion by an insulating layer, and a set of one or more bridging contacts in openings in the insulating layer. The bridging contacts electrically interconnect the top electrode portion and contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. Temperature concentration at the periphery of the openings is reduced by providing reduced thickness portions in the insulating layer around the periphery of the openings.

公开(公告)号：US20220139795A1

公开(公告)日：2022-05-05

申请号：US17580683

申请日：2022-01-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yohei YAMAGUCHI ,  Tomoyuki ASHIMINE ,  Yasuhiro MURASE

IPC: H01L23/31 ,  H01L49/02 ,  H01G4/33 ,  H01G4/224

Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface; a dielectric film on the first main surface, the dielectric film having an electrode layer disposing portion and a protective layer covering portion, and a thickness of the protective layer covering portion in a first outer peripheral end of the dielectric film is smaller than a thickness of the electrode layer disposing portion; a first electrode layer on the electrode layer disposing portion; a first protective layer covering a second outer peripheral end of the first electrode layer and at least a part of the protective layer covering portion; and a second protective layer covering the first protective layer, wherein the first protective layer has a relative permittivity lower than that of the second protective layer, and the second protective layer has moisture resistance higher than that of the first protective layer.

公开(公告)号：US20220181436A1

公开(公告)日：2022-06-09

申请号：US17651993

申请日：2022-02-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tomoyuki ASHIMINE ,  Yuji IRIE ,  Yasuhiro MURASE

IPC: H01L29/06 ,  H01L29/94 ,  H01L29/66

Abstract: A semiconductor device is provided that includes a semiconductor substrate having a first main surface and a second main surface facing each other; a dielectric layer laminated on the first main surface of the semiconductor substrate; a first electrode layer laminated on the dielectric layer; and a protective layer covering at least an outer peripheral end of the dielectric layer and an outer peripheral end of the first electrode layer. Moreover, the protective layer is provided to expose an outer peripheral end on the first main surface of the semiconductor substrate. The semiconductor substrate includes a high-resistance region positioned at least directly under an outer peripheral end of the protective layer.