中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.013 seconds)

    THROUGH-INTERPOSER GROUNDING USING BLIND VIAS
    1.
    发明申请
    THROUGH-INTERPOSER GROUNDING USING BLIND VIAS 有权

    公开(公告)号：US20220338349A1

    公开(公告)日：2022-10-20

    申请号：US17850495

    申请日：2022-06-27

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Stéphane BOUVIER ,  Emmanuel LEFEUVRE ,  Frédéric VOIRON

    IPC: H05K1/11 ,  H01S5/02315

    Abstract: A current path is provided through an interposer to ground a grounding pattern associated with a transmission line, by exploiting an interposer substrate that has a high-resistivity portion at a first surface and a low-resistivity portion extending from the high-resistivity portion to a second surface of the interposer. Moreover, a set of blind via-holes comprising electrically-conductive material extend from the first surface of the interposer substrate through the high-resistivity portion and into the low-resistivity portion. Top-to-bottom connection can be made using the conductive material in the blind vias and using the low-resistivity portion of the substrate, while the high-resistivity portion of the substrate impedes current leakage from the transmission line to the second surface of the substrate. The number and dimensions of the blind via-holes control the impedance of the grounding pattern relative to the transmission line's characteristic impedance.

    CONTACT STRUCTURES IN RC-NETWORK COMPONENTS
    3.
    发明申请
    CONTACT STRUCTURES IN RC-NETWORK COMPONENTS 有权

    公开(公告)号：US20230010467A1

    公开(公告)日：2023-01-12

    申请号：US17945462

    申请日：2022-09-15

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yohei YAMAGUCHI ,  Yasuhiro MURASE ,  Stéphane BOUVIER

    IPC: H01L27/01

    Abstract: RC-network components that include a substrate and capacitor having a thin-film top electrode portion at a surface on one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion by an insulating layer, and a set of one or more bridging contacts passing through openings in the insulating layer. The bridging contacts electrically interconnect the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The openings are elongated thereby reducing temperature concentration at their periphery. Correspondingly, the bridging contacts have an elongated cross-sectional shape.

    CONTACT STRUCTURES IN RC-NETWORK COMPONENTS
    4.
    发明申请
    CONTACT STRUCTURES IN RC-NETWORK COMPONENTS 有权

    公开(公告)号：US20230017133A1

    公开(公告)日：2023-01-19

    申请号：US17935296

    申请日：2022-09-26

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yohei YAMAGUCHI ,  Yasuhiro MURASE ,  Stéphane BOUVIER

    IPC: H01L27/06 ,  H01L27/01 ,  H01L29/94

    Abstract: RC-network components that include a substrate having a capacitor with a thin-film top electrode portion at a surface at one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance in series with the capacitor is controlled by providing a contact plate, spaced from the top electrode portion by an insulating layer, and a set of one or more bridging contacts in openings in the insulating layer. The bridging contacts electrically interconnect the top electrode portion and contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. Temperature concentration at the periphery of the openings is reduced by providing reduced thickness portions in the insulating layer around the periphery of the openings.

    3D CAPACITORS
    6.
    发明申请
    3D CAPACITORS 有权

    公开(公告)号：US20220216350A1

    公开(公告)日：2022-07-07

    申请号：US17656510

    申请日：2022-03-25

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Stéphane BOUVIER ,  Sébastien IOCHEM ,  David DENIS

    IPC: H01L29/94 ,  H01L29/66 ,  H01L49/02

    Abstract: A three-dimensional capacitor component that includes a substrate having a textured (contoured) surface and a stack of layers formed conformally over the textured surface to constitute a capacitive stack structure. Respective contacts to the bottom and top electrodes of the capacitive stack structure are both provided at a first side of the component. The bottom electrode and substrate are doped with dopants of the same polarity, and the substrate is heavily doped so that current between a terminal portion of the bottom electrode and remote parts of the bottom electrode flows via the substrate, lowering ESR. A backside metallization layer produces a further, and greater, reduction in ESR. The capacitor component may be implemented as a discrete capacitor component, but may also be integrated with other components/devices. Corresponding fabrication methods are described.

    ELECTRICAL DEVICE COMPRISING A 3D CAPACITOR AND A REGION SURROUNDED BY A THROUGH OPENING
    9.
    发明申请
    ELECTRICAL DEVICE COMPRISING A 3D CAPACITOR AND A REGION SURROUNDED BY A THROUGH OPENING 有权

    公开(公告)号：US20220190101A1

    公开(公告)日：2022-06-16

    申请号：US17551437

    申请日：2021-12-15

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Stéphane BOUVIER ,  Nicolas NORMAND ,  Emmanuel LEFEUVRE

    IPC: H01L49/02 ,  H01L23/522 ,  H01L27/08 ,  H01L21/768

    Abstract: An electrical device that includes a substrate; a 3D capacitor including a capacitor dielectric region of a dielectric material, a capacitor electrode region of a conductive material, the capacitor dielectric region and the capacitor electrode region being arranged at least partially inside a cavity extending in the substrate from a top face of the substrate; and a surrounding through opening in the substrate and which surrounds a surrounded substrate region, the 3D capacitor being outside of the surrounded substrate region, the surrounding through opening extending from the top face to a bottom face of the substrate, wherein inside the surrounding through opening a surrounding dielectric region of the dielectric material and a surrounding conductive region of the conductive material are arranged.

Patent Agency Ranking