公开(公告)号：US11056423B2

公开(公告)日：2021-07-06

申请号：US16411357

申请日：2019-05-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuichi Sano ,  Atsushi Kurokawa

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/367 ,  H01L23/00 ,  H01L23/34

Abstract: A semiconductor device includes a semiconductor chip mounted to a mounting substrate with an interposer interposed therebetween such that a surface of the semiconductor chip on which bumps are formed faces a surface of the mounting substrate. The mounting substrate has a plurality of metal parts formed as terminals on a surface of the mounting substrate and in contact with electrode pads connected to multilayer wiring. The semiconductor chip has a plurality of functional elements formed in an inner layer and a plurality of bumps formed in contact with element wiring lines of the functional elements such that the bumps protrude from the surface of the semiconductor chip. The interposer has a plurality of first recesses formed in the surface of the interposer facing the surface of the semiconductor chip on which the bumps are formed such that the first recesses accommodate only the bumps.

公开(公告)号：US20180145028A1

公开(公告)日：2018-05-24

申请号：US15814833

申请日：2017-11-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuya Kobayashi ,  Yuichi Sano ,  Daisuke Tokuda ,  Hiroaki Tokuya

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L23/3171 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53295 ,  H01L24/02

Abstract: A semiconductor device includes a semiconductor substrate, a first metal layer, an insulation layer, an organic layer, and a second metal layer. The first metal layer, the insulation layer, the organic layer, and the second metal layer are sequentially stacked on a surface of the semiconductor substrate. The first metal layer and the second metal layer are electrically connected to each other through vias formed in the insulation layer and the organic layer. The second metal layer includes an electrode pad at a position corresponding to the positions of the vias. At the interface between the surface of the semiconductor substrate and the first metal layer, a patch portion having a trapezoidal cross-sectional shape is disposed directly below the vias.

公开(公告)号：US11380601B2

公开(公告)日：2022-07-05

申请号：US16744525

申请日：2020-01-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi Kurokawa ,  Yuichi Sano ,  Toshihiro Tada

IPC: H01L21/56 ,  H01L21/3205 ,  H01L23/367 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor chip is mounted on a substrate in a face-down manner. A metal film is arranged on a back surface of the semiconductor chip facing an opposite side from the substrate away from an edge of the back surface. A sealing resin layer seals the semiconductor chip with a part of the metal film being exposed from the sealing resin layer.

公开(公告)号：US11335617B2

公开(公告)日：2022-05-17

申请号：US16744449

申请日：2020-01-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki Tokuya ,  Yuichi Sano ,  Toshihiro Tada

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56

Abstract: An electronic component whose reliability is less likely to decrease while its thermal conductivity is maintained. A semiconductor chip is mounted on a substrate. The semiconductor chip is sealed with a sealing resin layer. The sealing resin layer includes a binder and two types of fillers having a plurality of particles dispersed in the binder. As the two types of fillers, fillers at least one of whose physical quantities, which are average particle diameter and density, are different from each other are used. The total volume density of the fillers in the sealing resin layer decreases in an upward direction from the substrate, and a portion of the sealing resin layer in a height direction of the sealing resin layer has an area in which the two types of fillers are present in a mixed manner.

公开(公告)号：US10892350B2

公开(公告)日：2021-01-12

申请号：US16268557

申请日：2019-02-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi Kurokawa ,  Yuichi Sano

IPC: H01L29/737 ,  H01L27/082 ,  H01L29/417 ,  H01L29/08 ,  H01L25/07 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor element including a bipolar transistor disposed on a compound semiconductor substrate, a collector electrode, a base electrode, and an emitter electrode, the bipolar transistor including a collector layer, a base layer, and an emitter layer, the collector electrode being in contact with the collector layer, the base electrode being in contact with the base layer, the emitter electrode being in contact with the emitter layer; a protective layer disposed on one surface of the semiconductor element; an emitter redistribution layer electrically connected to the emitter electrode via a contact hole in the protective layer; and a stress-relieving layer disposed between the emitter redistribution layer and the emitter layer in a direction perpendicular to a surface of the compound semiconductor substrate.

公开(公告)号：US10950548B2

公开(公告)日：2021-03-16

申请号：US15903908

申请日：2018-02-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuichi Sano ,  Atsushi Kurokawa ,  Kazuya Kobayashi

IPC: H01L23/532 ,  H01L23/485

Abstract: A semiconductor device includes electrodes which contain Au and which are placed above conductive layers in a region adjacent to stacked insulating films and also includes base layers which are composed of compositionally modulated layers and which are placed between the electrodes and the conductive layers. The base layers include lateral end sections composed of single layers projecting from lateral end sections of the electrodes in the direction of the interlayer interface between the insulating films; sections which are located under the electrodes and of which a major compositional component is Ti or Ti and W; and projecting sections which project from under the electrodes in the direction of the interlayer interface between the insulating films and of which compositional components are compositionally modulated to Ti and O, to Ti, O, and N, or to Ti, W, O, and N.

公开(公告)号：US20200152536A1

公开(公告)日：2020-05-14

申请号：US16744449

申请日：2020-01-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki Tokuya ,  Yuichi Sano ,  Toshihiro Tada

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56

Abstract: An electronic component whose reliability is less likely to decrease while its thermal conductivity is maintained. A semiconductor chip is mounted on a substrate. The semiconductor chip is sealed with a sealing resin layer. The sealing resin layer includes a binder and two types of fillers having a plurality of particles dispersed in the binder. As the two types of fillers, fillers at least one of whose physical quantities, which are average particle diameter and density, are different from each other are used. The total volume density of the fillers in the sealing resin layer decreases in an upward direction from the substrate, and a portion of the sealing resin layer in a height direction of the sealing resin layer has an area in which the two types of fillers are present in a mixed manner.

公开(公告)号：US10121746B2

公开(公告)日：2018-11-06

申请号：US15814833

申请日：2017-11-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuya Kobayashi ,  Yuichi Sano ,  Daisuke Tokuda ,  Hiroaki Tokuya

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes a semiconductor substrate, a first metal layer, an insulation layer, an organic layer, and a second metal layer. The first metal layer, the insulation layer, the organic layer, and the second metal layer are sequentially stacked on a surface of the semiconductor substrate. The first metal layer and the second metal layer are electrically connected to each other through vias formed in the insulation layer and the organic layer. The second metal layer includes an electrode pad at a position corresponding to the positions of the vias. At the interface between the surface of the semiconductor substrate and the first metal layer, a patch portion having a trapezoidal cross-sectional shape is disposed directly below the vias.