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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11948986B2

    公开(公告)日：2024-04-02

    申请号：US17348811

    申请日：2021-06-16

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Atsushi Kurokawa ,  Masahiro Shibata ,  Hiroaki Tokuya ,  Mari Saji

    IPC: H01L29/417 ,  H01L29/08 ,  H01L29/73

    CPC classification number: H01L29/41708 ,  H01L29/0817 ,  H01L29/73

    Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.

    Electronic component
    2.
    发明授权
    Electronic component 有权

    公开(公告)号：US11335617B2

    公开(公告)日：2022-05-17

    申请号：US16744449

    申请日：2020-01-16

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Hiroaki Tokuya ,  Yuichi Sano ,  Toshihiro Tada

    IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56

    Abstract: An electronic component whose reliability is less likely to decrease while its thermal conductivity is maintained. A semiconductor chip is mounted on a substrate. The semiconductor chip is sealed with a sealing resin layer. The sealing resin layer includes a binder and two types of fillers having a plurality of particles dispersed in the binder. As the two types of fillers, fillers at least one of whose physical quantities, which are average particle diameter and density, are different from each other are used. The total volume density of the fillers in the sealing resin layer decreases in an upward direction from the substrate, and a portion of the sealing resin layer in a height direction of the sealing resin layer has an area in which the two types of fillers are present in a mixed manner.

    Semiconductor chip
    5.
    发明授权
    Semiconductor chip 有权

    公开(公告)号：US10559547B2

    公开(公告)日：2020-02-11

    申请号：US16006623

    申请日：2018-06-12

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Masahiro Shibata ,  Daisuke Tokuda ,  Atsushi Kurokawa ,  Hiroaki Tokuya ,  Yasunari Umemoto

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

    Abstract: A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface.

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180145028A1

    公开(公告)日：2018-05-24

    申请号：US15814833

    申请日：2017-11-16

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Kazuya Kobayashi ,  Yuichi Sano ,  Daisuke Tokuda ,  Hiroaki Tokuya

    IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532

    CPC classification number: H01L23/5283 ,  H01L23/3171 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53295 ,  H01L24/02

    Abstract: A semiconductor device includes a semiconductor substrate, a first metal layer, an insulation layer, an organic layer, and a second metal layer. The first metal layer, the insulation layer, the organic layer, and the second metal layer are sequentially stacked on a surface of the semiconductor substrate. The first metal layer and the second metal layer are electrically connected to each other through vias formed in the insulation layer and the organic layer. The second metal layer includes an electrode pad at a position corresponding to the positions of the vias. At the interface between the surface of the semiconductor substrate and the first metal layer, a patch portion having a trapezoidal cross-sectional shape is disposed directly below the vias.

    Power amplifier circuit and semiconductor device
    10.
    发明授权
    Power amplifier circuit and semiconductor device 有权

    公开(公告)号：US11601102B2

    公开(公告)日：2023-03-07

    申请号：US17168618

    申请日：2021-02-05

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Hiroaki Tokuya ,  Hideyuki Sato ,  Fumio Harima ,  Kenichi Shimamoto ,  Satoshi Tanaka ,  Takayuki Kawano ,  Ryoki Shikishima ,  Atsushi Kurokawa

    IPC: H03F1/30 ,  H03F3/24 ,  H01L23/00 ,  H03F3/195

    Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and configured to supply a bias current based on a first current which is a part of a control current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a part of the control current and an emitter configured to output a third current based on the second current; a first bump electrically connected to an emitter of the first transistor and disposed so as to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second bump disposed so as to overlap a second disposition area in which the third transistor is disposed in the plan view.

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