公开(公告)号：US06214648B1

公开(公告)日：2001-04-10

申请号：US09604762

申请日：2000-06-26

Applicant: Myeong Jin Shin

Inventor： Myeong Jin Shin

IPC: H01L2144

CPC classification number: H01L23/24 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1058 ,  H01L2924/1627 ,  H01L2924/00014

Abstract: The semiconductor chip package includes a package body with a recess and a plurality of barrier parts formed along one side thereof. Each of the barrier parts has a first region and a second region projecting from the first region, and adjacent first regions are separated by a slot. A semiconductor chip, including a reference surface having a circuit and a plurality of bonding pads formed thereon, is disposed in the recess of the package body. A conductive member is disposed in each slot, and a connecting member, associated with each bonding pad, electrically connects the associated bonding pad with a corresponding conductive member. A sealing member seals the semiconductor chip, the connecting members, and at least a portion of the conductive members in contact with the connecting members. Stacking these packages in the transverse and/or longitudinal direction further reduces their mounting area and increases the integrated capacity per unit of mounting area.

Abstract translation: 半导体芯片封装包括具有凹部的封装主体和沿其一侧形成的多个阻挡部。 每个阻挡部分具有从第一区域突出的第一区域和第二区域，并且相邻的第一区域被槽间隔开。 包括具有电路的参考表面和形成在其上的多个接合焊盘的半导体芯片设置在封装体的凹部中。 导电构件设置在每个槽中，并且与每个接合焊盘相关联的连接构件将相关联的焊盘与相应的导电构件电连接。 密封构件密封半导体芯片，连接构件以及与连接构件接触的至少一部分导电构件。 在横向和/或纵向上堆叠这些包装件进一步减小了它们的安装面积并且增加了每单位安装面积的集成容量。

公开(公告)号：US6140700A

公开(公告)日：2000-10-31

申请号：US966703

申请日：1997-11-10

Applicant: Myeong Jin Shin

Inventor： Myeong Jin Shin

IPC: H01L21/60 ,  H01L23/00 ,  H01L23/04 ,  H01L23/24 ,  H01L23/28 ,  H01L25/10

CPC classification number: H01L23/24 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1058 ,  H01L2924/1627

Abstract: The semiconductor chip package includes a package body with a recess and a plurality of barrier parts formed along one side thereof. Each of the barrier parts has a first region and a second region projecting from the first region, and adjacent first regions are separated by a slot. A semiconductor chip, including a reference surface having a circuit and a plurality of bonding pads formed thereon, is disposed in the recess of the package body. A conductive member is disposed in each slot, and a connecting member, associated with each bonding pad, electrically connects the associated bonding pad with a corresponding conductive member. A sealing member seals the semiconductor chip, the connecting members, and at least a portion of the conductive members in contact with the connecting members. Stacking these packages in the transverse and/or longitudinal direction further reduces their mounting area and increases the integrated capacity per unit of mounting area.

Abstract translation: 半导体芯片封装包括具有凹部的封装主体和沿其一侧形成的多个阻挡部。 每个阻挡部分具有从第一区域突出的第一区域和第二区域，并且相邻的第一区域被槽间隔开。 包括具有电路的参考表面和形成在其上的多个接合焊盘的半导体芯片设置在封装体的凹部中。 导电构件设置在每个槽中，并且与每个接合焊盘相关联的连接构件将相关联的焊盘与相应的导电构件电连接。 密封构件密封半导体芯片，连接构件以及与连接构件接触的至少一部分导电构件。 在横向和/或纵向上堆叠这些包装件进一步减小了它们的安装面积并且增加了每单位安装面积的集成容量。