公开(公告)号：US12087729B2

公开(公告)日：2024-09-10

申请号：US17406097

申请日：2021-08-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jen-Yuan Chang

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/20 ,  H01L23/24 ,  H01L23/31 ,  H01L25/00

CPC分类号： H01L25/0652 ,  H01L21/56 ,  H01L23/20 ,  H01L23/24 ,  H01L23/3135 ,  H01L23/315 ,  H01L25/50 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181

摘要： A semiconductor device includes a package substrate, and a first die group bonded onto the package substrate. The first die group characterized by a first thickness. The semiconductor device also has a second die group bonded onto the package substrate. The second die group characterized by a second thickness. The semiconductor device further includes a carrier substrate disposed on the first die group. The carrier substrate is characterized by a third thickness that is a function of a difference between the first thickness and the second thickness. A molding compound material is disposed on the package substrate and covers the first die group and the second die group. The molding compound material includes a cavity between the first die group and the second die group.

公开(公告)号：US20240297166A1

公开(公告)日：2024-09-05

申请号：US18664483

申请日：2024-05-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC分类号： H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L25/50 ,  H01L21/4803 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161

摘要： An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US20240290682A1

公开(公告)日：2024-08-29

申请号：US18658981

申请日：2024-05-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Shen Yeh ,  Yu-Sheng Lin ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC分类号： H01L23/367 ,  H01L23/24 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L23/3675 ,  H01L23/24 ,  H01L25/18 ,  H01L25/50

摘要： Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.

公开(公告)号：US11967540B2

公开(公告)日：2024-04-23

申请号：US17457100

申请日：2021-12-01

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Seungwon Im ,  Oseob Jeon ,  Byoungok Lee ,  Yoonsoo Lee ,  Joonseo Son ,  Dukyong Lee ,  Changyoung Park

IPC分类号： H01L25/065 ,  H01L23/13 ,  H01L23/433 ,  H01L23/473 ,  H01L23/495 ,  H01L23/498 ,  H01L23/24

CPC分类号： H01L23/433 ,  H01L23/13 ,  H01L23/4334 ,  H01L23/473 ,  H01L23/49568 ,  H01L23/49861 ,  H01L25/0657 ,  H01L23/24 ,  H01L2224/33

摘要： Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.

公开(公告)号：US20240079350A1

公开(公告)日：2024-03-07

申请号：US18457664

申请日：2023-08-29

申请人： Murata Manufacturing Co., Ltd.

发明人： Shigeru ENDO ,  Sami NURMI

IPC分类号： H01L23/00 ,  B81B7/00 ,  H01L23/24 ,  H01L23/498

CPC分类号： H01L23/562 ,  B81B7/0054 ,  H01L23/24 ,  H01L23/49811 ,  H01L23/3121

摘要： A packaging arrangement is provided that suppresses stress induced by extreme temperature changes during the process of attaching the electronic component. The arrangement includes adding to the package columnar conductors embedded in a solid support substance.

公开(公告)号：US11887904B2

公开(公告)日：2024-01-30

申请号：US17602634

申请日：2019-07-11

申请人： Mitsubishi Electric Corporation

发明人： Daisuke Oya

IPC分类号： H01L23/10 ,  H01L23/049 ,  H01L23/373 ,  H02P27/06 ,  H01L23/00 ,  H01L23/24

CPC分类号： H01L23/10 ,  H01L23/049 ,  H01L23/3735 ,  H01L23/24 ,  H01L24/73 ,  H02P27/06

摘要： It is an object to provide technology allowing for improvement in productivity of a semiconductor device. A semiconductor device includes: a base plate; an insulating substrate including a ceramic plate integrally bonded to an upper surface of the base plate with no solder layer therebetween and a circuit pattern disposed on an upper surface of the ceramic plate; a semiconductor element mounted on an upper surface of the circuit pattern; a case surrounding the insulating substrate and the semiconductor element over the base plate; an adhesive to adhere a lower portion of the case to an outer peripheral portion of the ceramic plate; and a sealant to seal the interior of the case, wherein the adhesive is in contact with an outer peripheral end of the ceramic plate to an outer peripheral end of the circuit pattern.

公开(公告)号：US11848319B2

公开(公告)日：2023-12-19

申请号：US17883878

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Chia Lai ,  Kuo Lung Pan ,  Hung-Yi Kuo ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/24 ,  H01L23/31 ,  H01L21/48

CPC分类号： H01L25/18 ,  H01L23/24 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L25/50 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3135 ,  H01L24/20 ,  H01L2224/02311 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/06155 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13024 ,  H01L2224/24101 ,  H01L2224/24147 ,  H01L2224/32147 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2924/14 ,  H01L2924/181

摘要： A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.

公开(公告)号：US11848213B2

公开(公告)日：2023-12-19

申请号：US17398461

申请日：2021-08-10

申请人： Infineon Technologies AG

发明人： Gopalakrishnan Trichy Rengarajan ,  Sebastian Michalski

IPC分类号： H01L21/54 ,  H01L23/31 ,  H01L23/24 ,  H01L23/29 ,  H01L25/07 ,  H01L23/498

CPC分类号： H01L21/54 ,  H01L23/24 ,  H01L23/295 ,  H01L23/3135 ,  H01L25/072 ,  H01L23/49811

摘要： A power semiconductor module arrangement includes: a substrate arranged within a housing; at least one semiconductor body arranged on a top surface of the substrate; and a first layer arranged on a first surface within the housing. The first layer includes inorganic filler which is impermeable to corrosive gases and a casting material which fills spaces present in the inorganic filler.

公开(公告)号：US20230395446A1

公开(公告)日：2023-12-07

申请号：US17829719

申请日：2022-06-01

申请人： Western Digital Technologies, Inc.

发明人： Yangming Liu ,  Shenghua Huang ,  Bo Yang ,  Ning Ye

IPC分类号： H01L23/24 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L23/24 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/0652 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/37001 ,  H01L2924/1438 ,  H01L2224/48148 ,  H01L2224/48229 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06593

摘要： A semiconductor device including one or more support structures for supporting a semiconductor-die stack having a region that overhangs a substrate. In an example embodiment, the support structures may be implemented using suitably shaped pieces of relatively thick round or ribbon wire attached to metal pads on the substrate. During the encapsulation operation, the one or more support structures may counteract a bending force applied to the semiconductor-die stack by a flow of the molding compound. At least some embodiments may beneficially be used, e.g., to enable high-yield fabrication of devices having sixteen or more stacked memory dies.

公开(公告)号：US11728233B2

公开(公告)日：2023-08-15

申请号：US16941847

申请日：2020-07-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Po-Chen Lai ,  Kuang-Chun Lee ,  Che-Chia Yang ,  Chin-Hua Wang ,  Yi-Hang Lin

IPC分类号： H01L23/24 ,  H01L23/498 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L23/24 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311

摘要： A method for forming a chip package structure is provided. The method includes disposing a first chip structure and a second chip structure over a wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The method includes disposing a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.