公开(公告)号：US08598010B2

公开(公告)日：2013-12-03

申请号：US13090553

申请日：2011-04-20

Applicant: Heung Jin Joo ,  JaeHee Oh ,  Byoungjae Bae ,  Myung Jin Kang

Inventor： Heung Jin Joo ,  JaeHee Oh ,  Byoungjae Bae ,  Myung Jin Kang

IPC: H01L21/02

CPC classification number: H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/1683

Abstract: Methods of forming a variable-resistance memory device include patterning an interlayer dielectric layer to define an opening therein that exposes a bottom electrode of a variable-resistance memory cell, on a memory cell region of a substrate (e.g., semiconductor substrate). These methods further include depositing a layer of variable-resistance material (e.g., phase-changeable material) onto the exposed bottom electrode in the opening and onto a first portion of the interlayer dielectric layer extending opposite a peripheral circuit region of the substrate. The layer of variable-resistance material and the first portion of the interlayer dielectric layer are then selectively etched in sequence to define a recess in the interlayer dielectric layer. The layer of variable-resistance material and the interlayer dielectric layer are then planarized to define a variable-resistance pattern within the opening.

Abstract translation: 形成可变电阻存储器件的方法包括图案化层间电介质层以限定其中可露出可变电阻存储单元的底部电极的开口，在衬底（例如，半导体衬底）的存储单元区域上。 这些方法还包括在开口中的暴露的底部电极上沉​​积可变电阻材料层（例如，相变材料），并且延伸到与衬底的外围电路区域相对延伸的层间电介质层的第一部分上。 然后依次选择性地蚀刻可变电阻材料层和层间电介质层的第一部分，以在层间介质层中限定凹陷。 然后将可变电阻材料层和层间电介质层平坦化，以在开口内限定可变电阻图案。

公开(公告)号：US08765564B2

公开(公告)日：2014-07-01

申请号：US13495529

申请日：2012-06-13

Applicant: Myung Jin Kang

Inventor： Myung Jin Kang

IPC: H01L21/20 ,  H01L45/00

CPC classification number: H01L45/1683 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

Abstract: A method of forming a variable resistive memory device includes forming a conductive pattern that alternates with a first insulation pattern along a first direction on a substrate that is parallel with a surface of the substrate, forming a preliminary sacrificial pattern on the conductive pattern that contacts a sidewall of the first insulation pattern, etching the conductive pattern using the preliminary sacrificial pattern as an etch masks to form a preliminary bottom electrode pattern, patterning the preliminary sacrificial pattern and the preliminary bottom electrode pattern to form a sacrificial pattern and a bottom electrode pattern that each include at least two portions which are separated from each other along a second direction intersecting the first direction, and replacing the sacrificial pattern with a variable resistive pattern.

Abstract translation: 一种形成可变电阻式存储器件的方法包括：在与衬底的表面平行的衬底上沿第一方向形成与第一绝缘图案交替的导电图案，在与衬底的表面平行的衬底上形成初步牺牲图案， 第一绝缘图案的侧壁，使用预备牺牲图案蚀刻导电图案作为蚀刻掩模以形成初步底部电极图案，图案化初步牺牲图案和预备底部电极图案以形成牺牲图案和底部电极图案， 每个包括沿着与第一方向相交的第二方向彼此分离的至少两个部分，并且以可变电阻图案替换牺牲图案。

公开(公告)号：US08653493B2

公开(公告)日：2014-02-18

申请号：US13369662

申请日：2012-02-09

Applicant: Myung Jin Kang ,  Youngnam Hwang

Inventor： Myung Jin Kang ,  Youngnam Hwang

IPC: H01L29/02

CPC classification number: H01L45/1683 ,  H01L27/2409 ,  H01L45/06

Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.

Abstract translation: 根据示例实施例，可变电阻存储器件在衬底上包括欧姆图案; 第一电极图案，包括具有板形并接触欧姆图案的顶表面的第一部分和从第一部分的一端延伸到顶部的第二部分; 电连接到第一电极图案的可变电阻图案; 以及电连接到所述可变电阻图案的第二电极图案，其中所述欧姆图案的一端和所述第一部分的另一端设置在同一平面上。

公开(公告)号：US20120211720A1

公开(公告)日：2012-08-23

申请号：US13369662

申请日：2012-02-09

Applicant: Myung Jin Kang ,  Youngnam Hwang

Inventor： Myung Jin Kang ,  Youngnam Hwang

IPC: H01L47/00

CPC classification number: H01L45/1683 ,  H01L27/2409 ,  H01L45/06

Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.

Abstract translation: 根据示例实施例，可变电阻存储器件在衬底上包括欧姆图案; 第一电极图案，包括具有板形并接触欧姆图案的顶表面的第一部分和从第一部分的一端延伸到顶部的第二部分; 电连接到第一电极图案的可变电阻图案; 以及电连接到所述可变电阻图案的第二电极图案，其中所述欧姆图案的一端和所述第一部分的另一端设置在同一平面上。

公开(公告)号：US20110263093A1

公开(公告)日：2011-10-27

申请号：US13090553

申请日：2011-04-20

Applicant: Heung Jin Joo ,  JaeHee Oh ,  Byoungjae Bae ,  Myung Jin Kang

Inventor： Heung Jin Joo ,  JaeHee Oh ,  Byoungjae Bae ,  Myung Jin Kang

IPC: H01L21/02

CPC classification number: H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/1683

Abstract: Methods of forming a variable-resistance memory device include patterning an interlayer dielectric layer to define an opening therein that exposes a bottom electrode of a variable-resistance memory cell, on a memory cell region of a substrate (e.g., semiconductor substrate). These methods further include depositing a layer of variable-resistance material (e.g., phase-changeable material) onto the exposed bottom electrode in the opening and onto a first portion of the interlayer dielectric layer extending opposite a peripheral circuit region of the substrate. The layer of variable-resistance material and the first portion of the interlayer dielectric layer are then selectively etched in sequence to define a recess in the interlayer dielectric layer. The layer of variable-resistance material and the interlayer dielectric layer are then planarized to define a variable-resistance pattern within the opening.

Abstract translation: 形成可变电阻存储器件的方法包括图案化层间电介质层以限定其中可露出可变电阻存储单元的底部电极的开口，在衬底（例如，半导体衬底）的存储单元区域上。 这些方法还包括在开口中的暴露的底部电极上沉​​积可变电阻材料层（例如，相变材料），并且延伸到与衬底的外围电路区域相对延伸的层间电介质层的第一部分上。 然后依次选择性地蚀刻可变电阻材料层和层间电介质层的第一部分，以在层间介质层中限定凹陷。 然后将可变电阻材料层和层间电介质层平坦化，以在开口内限定可变电阻图案。