公开(公告)号：US20190198758A1

公开(公告)日：2019-06-27

申请号：US16284932

申请日：2019-02-25

申请人： Arm Limited

发明人： Carlos Alberto Paz de Araujo ,  Jolanta Bozena Celinska ,  Christopher Randolph McWilliams ,  Lucian Shifren ,  Kimberly Gay Reid

IPC分类号： H01L45/00

CPC分类号： H01L45/1608 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1633 ,  H01L45/1641 ,  H01L45/1658

摘要： Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described in which a correlated electron material film may be formed over a conductive substrate by converting at least a portion of the conductive substrate to CEM.

公开(公告)号：US20190057739A1

公开(公告)日：2019-02-21

申请号：US16153143

申请日：2018-10-05

申请人： Micron Technology, Inc.

发明人： Jun Liu

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C5/06 ,  G11C5/063 ,  G11C11/4097 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

摘要： A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

公开(公告)号：US20190051826A1

公开(公告)日：2019-02-14

申请号：US16164510

申请日：2018-10-18

申请人： Micron Technology, Inc.

发明人： Thomas R. Omstead ,  Cole S. Franklin

IPC分类号： H01L45/00 ,  C23C16/36 ,  C23C16/455 ,  H01L21/02 ,  C23C16/34 ,  H01L27/24 ,  H01L21/283 ,  H01L21/768

CPC分类号： H01L45/124 ,  C23C16/345 ,  C23C16/36 ,  C23C16/45534 ,  C23C16/45542 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/283 ,  H01L21/76829 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/16

摘要： A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.

公开(公告)号：US20180350879A1

公开(公告)日：2018-12-06

申请号：US15610918

申请日：2017-06-01

申请人： SANDISK TECHNOLOGIES LLC

发明人： Jongsun Sel ,  Tuan Pham ,  Mitsuteru Mushiga ,  Yoshihiro Ikeda ,  Daewung Kang ,  Akio Nishida

IPC分类号： H01L27/24 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/768 ,  H01L45/00

CPC分类号： H01L27/2481 ,  H01L21/76879 ,  H01L23/5226 ,  H01L27/1157 ,  H01L27/11582 ,  H01L45/16

摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory structures, conductive structures located between a substrate and the alternating stack, conductive via structures, including an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers, and a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from the rest of the electrically conductive layers. Inner, outer and intermediate dielectric spacers laterally surround a respective one of the conductive via structures.

公开(公告)号：US20180331282A1

公开(公告)日：2018-11-15

申请号：US15594498

申请日：2017-05-12

申请人： United Microelectronics Corp.

发明人： Mengkai Zhu

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1233 ,  G11C13/0002 ,  G11C2213/52 ,  H01L27/2409 ,  H01L45/1253 ,  H01L45/16

摘要： A resistive random access memory (RRAM) structure including a substrate, RRAM cells and protection layers is provided. The RRAM cells are adjacent to each other and disposed on the substrate. The protection layers are disposed respectively on sidewalls of the RRAM cells without covering top surfaces of the RRAM cells. Each of the protection layers includes a sidewall portion and an extension portion. The sidewall portion is disposed on each of the sidewalls of each of the RRAM cells. The extension portion is connected to a lower portion of the sidewall portion. An upper portion of the extension portion is lower than an upper portion of the sidewall portion. The extension portion is connected between the sidewall portions in a region between the RRAM cells.

公开(公告)号：US20180277602A1

公开(公告)日：2018-09-27

申请号：US15987613

申请日：2018-05-23

申请人： Micron Technology, Inc.

发明人： Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1666 ,  H01L45/1691

摘要： A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US10079340B2

公开(公告)日：2018-09-18

申请号：US15090292

申请日：2016-04-04

申请人： Micron Technology, Inc.

发明人： Tsz W. Chan ,  Yongjun Jeff Hu ,  Swapnil Lengade ,  Shu Qin ,  Everett Allen McTeer

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165 ,  H01L45/1675

摘要： Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

公开(公告)号：US20180261766A1

公开(公告)日：2018-09-13

申请号：US15452373

申请日：2017-03-07

申请人： SANDISK TECHNOLOGIES LLC

发明人： Ming-Che Wu ,  Deepak Kamalanathan ,  Juan Saenz ,  Tanmay Kumar

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1608 ,  G11C7/18 ,  G11C8/14 ,  G11C13/0007 ,  G11C2213/35 ,  G11C2213/71 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/146 ,  H01L45/16

摘要： A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line includes a first portion and a second portion including an electrically conductive carbon-containing material. The nonvolatile memory material includes a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer disposed adjacent the second portion of the word line.

公开(公告)号：US10074802B2

公开(公告)日：2018-09-11

申请号：US15365378

申请日：2016-11-30

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Claire Fenouillet-Beranger ,  Elisa Vianello

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1683 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

摘要： Method for producing a device with transistors distributed over several levels and provided with a resistive memory cell having an electrode formed of a conductor portion belonging to a connection element connected to a transistor of a given level.

公开(公告)号：US20180248117A1

公开(公告)日：2018-08-30

申请号：US15962546

申请日：2018-04-25

申请人： Provenance Asset Group LLC

发明人： Alexander Alexandrovich Bessonov ,  Dmitrii Igorevich Petukhov ,  Marina Nikolaevna Kirikova ,  Mark Bailey ,  Tapani Ryhanen

IPC分类号： H01L45/00 ,  H01G7/06

CPC分类号： H01L45/1233 ,  H01G7/06 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/141 ,  H01L45/142 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1641

摘要： A device is disclosed which comprises a first electrode (101), a second electrode (104) spaced from the first electrode, a switching region (102) positioned between the first electrode and the second electrode, and an intermediate region (103) positioned between the switching region and the second electrode, wherein the intermediate region is in electrical contact with the switching region and the second electrode. Preferably, the intermediate region comprises metal nanowires (105) in a polymer matrix, and the device is a memristor or a memcapacitor. In the latter case, the switching region comprises a conductive material (106) and an insulating material (107).