公开(公告)号：US20120228577A1

公开(公告)日：2012-09-13

申请号：US13416553

申请日：2012-03-09

Applicant: Kyusul PARK ,  JaeHee OH ,  Heung Jin JOO

Inventor： Kyusul PARK ,  JaeHee OH ,  Heung Jin JOO

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A phase change memory device includes a mold oxide layer on a substrate, a lower electrode on the mold oxide layer and connected to the substrate, a blocking structure covering a part of the lower electrode and including an etch-stop layer and a blocking structure insulating layer, and a phase change layer covering a remaining part of the lower electrode not covered by the blocking structure, The etch-stop layer includes a material having a higher etching selectivity than that of the lower electrode.

Abstract translation: 相变存储装置包括在基板上的模具氧化物层，在模具氧化物层上的下电极并连接到基板，覆盖下电极的一部分的阻挡结构，包括蚀刻停止层和绝缘层 层，以及覆盖未被阻挡结构覆盖的下部电极的剩余部分的相变层。蚀刻停止层包括具有比下部电极的蚀刻选择性更高的蚀刻选择性的材料。

公开(公告)号：US20110248235A1

公开(公告)日：2011-10-13

申请号：US13081168

申请日：2011-04-06

Applicant: Ji-Hyun Jeong ,  JaeHee Oh ,  Heung Jin Joo ,  Sung-Ho Eun

Inventor： Ji-Hyun Jeong ,  JaeHee Oh ,  Heung Jin Joo ,  Sung-Ho Eun

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144

Abstract: A nonvolatile memory device includes a substrate and a first insulating layer on the substrate. The first insulating layer includes a first opening therein. A lower electrode is provided in the first opening and protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation pattern is provided on a sidewall of the lower electrode that protrudes from the surface of the first insulating layer. A second insulating layer is provided on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. A variable resistance material layer extends into the second opening to contact the lower electrode. The electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer. The electrode passivation pattern is formed of a material having an etching selectivity to that of the second insulating layer. Related fabrication methods are also discussed.

Abstract translation: 非易失性存储器件包括衬底和衬底上的第一绝缘层。 第一绝缘层包括其中的第一开口。 下电极设置在第一开口中并从第一开口外侧的第一绝缘层的表面突出。 电极钝化图案设置在从第一绝缘层的表面突出的下电极的侧壁上。 第二绝缘层设置在第一绝缘层上，并且包括其中至少部分地暴露下电极的第二开口。 可变电阻材料层延伸到第二开口中以接触下电极。 电极钝化层将下电极的侧壁与可变电阻材料层电隔离。 电极钝化图案由具有对第二绝缘层的蚀刻选择性的蚀刻选择性的材料形成。 还讨论了相关的制造方法。

公开(公告)号：US20100173479A1

公开(公告)日：2010-07-08

申请号：US12652451

申请日：2010-01-05

Applicant: Heung Jin Joo

Inventor： Heung Jin Joo

IPC: H01L47/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1691

Abstract: Provided are variable resistance memory devices and methods of forming the variable resistance memory devices. The methods can include forming an etch stop layer on an electrode, forming a molding layer on the etch stop layer, forming a recess region including a lower part having a first width and an upper part having a second width by recessing the etch stop layer and the molding layer, and forming a layer of variable resistance material in the recess region.

Abstract translation: 提供了可变电阻存储器件和形成可变电阻存储器件的方法。 所述方法可以包括在电极上形成蚀刻停止层，在蚀刻停止层上形成模制层，通过凹陷蚀刻停止层形成包括具有第一宽度的下部和具有第二宽度的上部的凹陷区域，以及 所述成型层，并且在所述凹部区域中形成可变电阻材料层。

公开(公告)号：US07105418B2

公开(公告)日：2006-09-12

申请号：US10997408

申请日：2004-11-24

Applicant: Heung-Jin Joo

Inventor： Heung-Jin Joo

IPC: H01L21/20

CPC classification number: H01L28/91 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/55

Abstract: For forming stacked capacitors, an opening is formed through at least one semiconductor material. A lower electrode material is patterned within the opening to form a plurality of lower electrodes within the opening. The stacked capacitors are formed with the lower electrodes within the opening by depositing a capacitor dielectric and an upper electrode within the opening. With such a relatively large opening, a capacitor dielectric of the stacked capacitors is deposited with a large thickness for improving reliability of the stacked capacitors.

Abstract translation: 为了形成叠层电容器，通过至少一种半导体材料形成开口。 在开口内图案化下电极材料，以在开口内形成多个下电极。 堆叠的电容器通过在开口内沉积电容器电介质和上电极而在开口内由下电极形成。 通过这样一个比较大的开口，叠层电容器的电容器电介质被沉积成较大的厚度，以提高叠层电容器的可靠性。

公开(公告)号：US20060108622A1

公开(公告)日：2006-05-25

申请号：US11248629

申请日：2005-10-12

Applicant: Heung-jin Joo ,  Ki-nam Kim ,  Yoon-jong Song

Inventor： Heung-jin Joo ,  Ki-nam Kim ,  Yoon-jong Song

IPC: H01L29/94 ,  H01L21/00

CPC classification number: H01L28/55 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/57

Abstract: Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.

公开(公告)号：US20060006447A1

公开(公告)日：2006-01-12

申请号：US11180954

申请日：2005-07-12

Applicant: Hyun-Ho Kim ,  Heung-Jin Joo ,  Ki-Nam Kim

Inventor： Hyun-Ho Kim ,  Heung-Jin Joo ,  Ki-Nam Kim

IPC: H01L27/108

CPC classification number: H01L28/75 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/91

Abstract: A semiconductor device having an MIM capacitor and a method of forming the same are provided. A lower electrode includes a plate electrode and a sidewall electrode. The plate electrode is formed by a patterning process preferably including a plasma anisotropic etching. The sidewall electrode is formed like a spacer on an inner sidewall of an opening exposing the plate electrode by a plasma entire surface anisotropic etching.

公开(公告)号：US08748884B2

公开(公告)日：2014-06-10

申请号：US13081168

申请日：2011-04-06

Applicant: Ji-Hyun Jeong ,  JaeHee Oh ,  Heung Jin Joo ,  Sung-Ho Eun

Inventor： Ji-Hyun Jeong ,  JaeHee Oh ,  Heung Jin Joo ,  Sung-Ho Eun

IPC: H01L29/12

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144

Abstract: A nonvolatile memory device includes a substrate and a first insulating layer on the substrate. The first insulating layer includes a first opening therein. A lower electrode is provided in the first opening and protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation pattern is provided on a sidewall of the lower electrode that protrudes from the surface of the first insulating layer. A second insulating layer is provided on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. A variable resistance material layer extends into the second opening to contact the lower electrode. The electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer. The electrode passivation pattern is formed of a material having an etching selectivity to that of the second insulating layer. Related fabrication methods are also discussed.

Abstract translation: 非易失性存储器件包括衬底和衬底上的第一绝缘层。 第一绝缘层包括其中的第一开口。 下电极设置在第一开口中并从第一开口外侧的第一绝缘层的表面突出。 电极钝化图案设置在从第一绝缘层的表面突出的下电极的侧壁上。 第二绝缘层设置在第一绝缘层上，并且包括其中至少部分地暴露下电极的第二开口。 可变电阻材料层延伸到第二开口中以接触下电极。 电极钝化层将下电极的侧壁与可变电阻材料层电隔离。 电极钝化图案由具有对第二绝缘层的蚀刻选择性的蚀刻选择性的材料形成。 还讨论了相关的制造方法。

公开(公告)号：US20110188292A1

公开(公告)日：2011-08-04

申请号：US12972945

申请日：2010-12-20

Applicant: Heung Jin JOO ,  Jae Hee OH ,  Sung-Ho EUN

Inventor： Heung Jin JOO ,  Jae Hee OH ,  Sung-Ho EUN

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79

Abstract: Provided is an operating method of a variable resistance memory device. The operating method applies a set pulse to a plurality of memory cells to be written in a set state, and applies a reset pulse to a plurality of memory cells to be written in a reset state. The width of the set pulse is narrower than the width of the reset pulse.

Abstract translation: 提供了一种可变电阻存储器件的操作方法。 操作方法将设置脉冲施加到要设置状态的多个存储单元，并将复位脉冲施加到多个存储单元以写入复位状态。 设定脉冲的宽度比复位脉冲的宽度窄。

公开(公告)号：US20080111171A1

公开(公告)日：2008-05-15

申请号：US11811931

申请日：2007-06-12

Applicant: Heung-Jin Joo ,  Yoon-Jong Song ,  Ki-Nam Kim

Inventor： Heung-Jin Joo ,  Yoon-Jong Song ,  Ki-Nam Kim

IPC: H01L29/94 ,  H01L21/02

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55

Abstract: In a node structure under a capacitor in a ferroelectric random access memory device and a method of forming the same, top surfaces of the node structures are disposed at substantially the same level as a top surface of an interlayer insulating layer surrounding the node structures, and thus crystal growth of a ferroelectric in the capacitor can be stabilized. To this end, a node insulating pattern is formed on a semiconductor substrate. A node defining pattern surrounding the node insulating pattern is disposed under the node insulating pattern. A node conductive pattern is disposed between the node defining pattern and the node insulating pattern.

Abstract translation: 在铁电随机存取存储器件中的电容器下的节点结构及其形成方法中，节点结构的顶表面设置在与节点结构周围的层间绝缘层的顶表面基本相同的水平处，并且 因此可以使电容器中的铁电体的晶体生长稳定。 为此，在半导体衬底上形成节点绝缘图案。 定义节点绝缘图案周围的节点的节点设置在节点绝缘图案之下。 节点导电图案设置在节点限定图案和节点绝缘图案之间。

公开(公告)号：US20080061334A1

公开(公告)日：2008-03-13

申请号：US11896952

申请日：2007-09-07

Applicant: Ju-Young Jung ,  Suk-Ho Joo ,  Jung-Hoon Park ,  Heung-Jin Joo ,  Hee-San Kim ,  Seung-Kuk Kang ,  Do-Yeon Choi

Inventor： Ju-Young Jung ,  Suk-Ho Joo ,  Jung-Hoon Park ,  Heung-Jin Joo ,  Hee-San Kim ,  Seung-Kuk Kang ,  Do-Yeon Choi

IPC: H01L29/94 ,  H01L21/02

CPC classification number: H01L27/11507 ,  H01L21/76849 ,  H01L21/7687 ,  H01L23/5226 ,  H01L27/11502 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and a method for forming the same. The method includes forming an insulating layer on a semiconductor substrate having a conductive region, forming a contact hole that exposes the conductive region by etching the insulating layer, forming a barrier metal layer that covers a sidewall and a bottom of the contact hole, and forming a contact plug in the contact hole by interposing the barrier metal layer therebetween. An etching process may be preformed that recesses the barrier metal layer and the contact plug in such a manner that a top surface of the contact plug protrudes upward beyond a top surface of the barrier metal layer. A capping plug may be formed covering the recessed barrier metal layer and the recessed contact plug. A capacitor may be formed on the capping plug.

Abstract translation: 一种半导体存储器件及其形成方法。 该方法包括在具有导电区域的半导体衬底上形成绝缘层，形成通过蚀刻绝缘层而暴露导电区域的接触孔，形成覆盖接触孔的侧壁和底部的阻挡金属层，以及形成 通过在其间插入阻挡金属层，在接触孔中形成接触塞。 可以进行蚀刻工艺，其以使得接触插头的顶表面向上突出超过阻挡金属层的顶表面的方式使阻挡金属层和接触插塞凹陷。 可以形成覆盖凹陷的阻挡金属层和凹入的接触插塞的封盖塞。 可以在封盖上形成电容器。