公开(公告)号：US3626298A

公开(公告)日：1971-12-07

申请号：US3626298D

申请日：1969-07-08

Applicant: NASA

Inventor： ANDERSON TAGE O ,  HURD WILLIAM J ,  LINDSEY WILLIAM C

IPC: H04L7/033 ,  H04B7/18 ,  H04B7/20 ,  H04L7/02

CPC classification number: H04L7/0332

Abstract: A bit synchronization system, incorporating a digital data transition tracking phase-locked loop. The system, to which an input signal in the form of a noise-distorted constant amplitude bipolar stream of data bits, is assumed to be supplied, includes two integration channels. In one channel integrations are performed over assumed bit times, each bit time being equal to a bit period, while in the other channel integrations are performed over integration windows, each window being less than a bit period. The outputs of the two channels are combined to provide a pair of binary signals which are supplied to a digital filter, comprising a variable length counter and a variable gain register. The contents of two registers are combined to provide an error signal indicative of the direction of the phase difference between periods of bits in said stream and the assumed bit times.