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公开(公告)号：US3632996A
公开(公告)日：1972-01-04
申请号：US3632996D
申请日：1970-05-14
Applicant: NASA
Inventor： ANDERSON TAGE O , HURD WILLIAM J
CPC classification number: G06F1/02 , G06F7/68 , G06F2101/10 , H03K23/667
Abstract: A quasi-exponential function generator comprising a multistage counter which is clocked at a rate which is a function of the count or value of the counter. The possible counts are divided into fields which are sensed and the clock rate is reduced by a factor of two, as the count changes from one field to a lower field. Each field is further divided into several subfields which are also detected to control the clock rate to vary from subfield to subfield.
Abstract translation: 准指数函数发生器，其包括以与计数器的计数或值的函数对应的速率计时的多级计数器。 可能的计数被划分为被感测的场，并且时钟速率被减少了2倍，因为计数从一个场改变到较低的场。 每个场进一步划分为几个子场，这些子场也被检测为控制从子场到子场的时钟速率。
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公开(公告)号：US3626298A
公开(公告)日：1971-12-07
申请号：US3626298D
申请日：1969-07-08
Applicant: NASA
Inventor： ANDERSON TAGE O , HURD WILLIAM J , LINDSEY WILLIAM C
CPC classification number: H04L7/0332
Abstract: A bit synchronization system, incorporating a digital data transition tracking phase-locked loop. The system, to which an input signal in the form of a noise-distorted constant amplitude bipolar stream of data bits, is assumed to be supplied, includes two integration channels. In one channel integrations are performed over assumed bit times, each bit time being equal to a bit period, while in the other channel integrations are performed over integration windows, each window being less than a bit period. The outputs of the two channels are combined to provide a pair of binary signals which are supplied to a digital filter, comprising a variable length counter and a variable gain register. The contents of two registers are combined to provide an error signal indicative of the direction of the phase difference between periods of bits in said stream and the assumed bit times.
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3.发明授权
公开(公告)号：US3579122A
公开(公告)日：1971-05-18
申请号：US3579122D
申请日：1969-12-23
Applicant: NASA
Inventor： ANDERSON TAGE O , HURD WILLIAM J
CPC classification number: H03H17/0223 , H03C3/00
Abstract: A digital filter comprising two up-down counters A and B. Counter A which is responsive to a sampled input signal which is quantized into three levels +1, -1 and 0, is incremented in response to each +1 input, decremented in response to each -1 input, and remains unchanged in response to a 0 input. Counter B, which includes N stages, is incremented at each sampling time when A is positive, decremented when A is negative and remains unchanged when A is zero. When B overflows in a positive direction A is decremented by one while a negative overflow of B results in A being incremented by one. The filter output is +2 N when A is positive, -2 N when A is negative and zero (0) when the count in A is zero.
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