公开(公告)号：US20240213364A1

公开(公告)日：2024-06-27

申请号：US18556293

申请日：2022-04-15

Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Yoshinao MIURA ,  Akira NAKAJIMA ,  Xu-Qiang SHEN ,  Hirohisa HIRAI ,  Shinsuke HARADA

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/20 ,  H01L29/861

CPC classification number: H01L29/7811 ,  H01L21/265 ,  H01L29/2003 ,  H01L29/7813 ,  H01L29/8613

Abstract: There is provided a semiconductor equipment including: an element area having an n-type layer, a first p-type layer on the n-type layer, and a second p-type layer on the first p-type layer, the second p-type layer having an acceptor concentration higher than the first p-type layer; and an electric field relaxation region surrounding the element area, in which in the electric field relaxation region, a region containing an impurity element that inactivates a part of acceptors in the first p-type layer and the second p-type layer is provided in the first p-type layer and the second p-type layer.