Method and circuit for deriving a second clock signal from a first clock signal
    1.
    发明申请
    Method and circuit for deriving a second clock signal from a first clock signal 有权
    用于从第一时钟信号导出第二时钟信号的方法和电路

    公开(公告)号:US20020039396A1

    公开(公告)日:2002-04-04

    申请号:US09968524

    申请日:2001-10-02

    Inventor: Filip Zalio

    CPC classification number: G06F1/0328

    Abstract: A clock generation circuit (21) for a dual system radio frequency (RF) station, including: a digital synthesis circuit (20) clocked by a first clock signal for one RF system and adapted to generate an output having a base signal of a predetermined frequency; and filter means (31) for deriving a second clock signal for another RF system from a signal of said output, said signal having a frequency corresponding to the frequency of said second clock signal.

    Abstract translation: 一种用于双系统射频(RF)站的时钟发生电路(21),包括:数字合成电路(20),其由一个RF系统的第一时钟信号计时,并且适于产生具有预定 频率; 以及用于从所述输出的信号导出另一RF系统的第二时钟信号的滤波器装置(31),所述信号具有对应于所述第二时钟信号的频率的频率。

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