公开(公告)号：US20200021367A1

公开(公告)日：2020-01-16

申请号：US16583437

申请日：2019-09-26

Applicant: NEC Corporation

Inventor： Daisaku OGASAHARA ,  Junichi ABE

IPC: H04B10/61 ,  H04B10/079

Abstract: When a frequency deviation compensation amount is compensated for by use of frequency shift, a phase offset occurs between adjacent input blocks included in a plurality of input blocks as divided, with the result that an error occurs in a reconstructed bit sequence. A frequency deviation compensation system of the invention is characterized by comprising: a frequency deviation compensation means for compensating for a frequency deviation occurring in a signal by use of frequency shift; and a phase offset compensation means for compensating for a phase offset occurring, in the signal, due to the frequency shift.

公开(公告)号：US20160285562A1

公开(公告)日：2016-09-29

申请号：US15033955

申请日：2014-10-23

Applicant: NEC CORPORATION

Inventor： Daisaku OGASAHARA ,  Junichi ABE

IPC: H04B10/61 ,  H04L27/26 ,  H04B10/079

CPC classification number: H04B10/6164 ,  H04B10/0795 ,  H04B10/6165 ,  H04L27/265

Abstract: When a frequency deviation compensation amount is compensated for by use of frequency shift, a phase offset occurs between adjacent input blocks included in a plurality of input blocks as divided, with the result that an error occurs in a reconstructed bit sequence. A frequency deviation compensation system of the invention is characterized by comprising: a frequency deviation compensation means for compensating for a frequency deviation occurring in a signal by use of frequency shift; and a phase offset compensation means for compensating for a phase offset occurring, in the signal, due to the frequency shift.

Abstract translation: 当通过使用频率补偿频率偏移补偿量时，在分割的多个输入块中包括的相邻输入块之间发生相位偏移，结果是在重构的比特序列中出现错误。 本发明的频偏补偿系统的特征在于包括：频偏补偿装置，用于通过使用频移补偿信号中发生的频偏; 以及相位偏移补偿装置，用于补偿在信号中由于频率偏移而发生的相位偏移。

公开(公告)号：US20240388307A1

公开(公告)日：2024-11-21

申请号：US18658328

申请日：2024-05-08

Applicant: NEC Corporation

Inventor： Daisaku OGASAHARA ,  Masaaki Tanio

IPC: H03M3/00

Abstract: A processing apparatus includes: a distribution unit that divides an input signal into input signal blocks, and distributes, in dividing order, the divided input signal blocks to delta-sigma modulation circuits; a parallel circuit unit including the delta-sigma modulation circuits that perform delta-sigma modulation on the input signal blocks and output output signal blocks; and a coupling unit that couples the output signal blocks outputted from the parallel circuit unit, thereby to generate an output signal such that a first output signal block reflects a result obtained from a first delta-sigma modulation circuit, which performs delta-sigma modulation on a first input signal block corresponding to the first output signal block, performing delta-sigma modulation on the first input signal block, and a state of a second delta-sigma modulation circuit that performs delta-sigma modulation on a second input signal block located immediately before or after the first input signal block.

公开(公告)号：US20230119734A1

公开(公告)日：2023-04-20

申请号：US18084814

申请日：2022-12-20

Applicant: NEC Corporation

Inventor： Daisaku OGASAHARA ,  Junichi ABE

IPC: H04B10/61 ,  H04L27/26 ,  H04B10/079

Abstract: When a frequency deviation compensation amount is compensated for by use of frequency shift, a phase offset occurs between adjacent input blocks included in a plurality of input blocks as divided, with the result that an error occurs in a reconstructed bit sequence. A frequency deviation compensation system of the invention is characterized by comprising: a frequency deviation compensation means for compensating for a frequency deviation occurring in a signal by use of frequency shift; and a phase offset compensation means for compensating for a phase offset occurring, in the signal, due to the frequency shift.

公开(公告)号：US20250158636A1

公开(公告)日：2025-05-15

申请号：US18934345

申请日：2024-11-01

Applicant: NEC Corporation

Inventor： Daisaku OGASAHARA ,  Masaaki TANIO

IPC: H03M3/00

Abstract: A delta-sigma modulation apparatus divides an input signal into a plurality of signal blocks, inputs the plurality of signal blocks to a plurality of delta-sigma modulation circuits, and performs combining processing for combining a plurality of output signals from the plurality of delta-sigma modulation circuits.

公开(公告)号：US20160183211A1

公开(公告)日：2016-06-23

申请号：US14910039

申请日：2014-07-22

Applicant: NEC CORPORATION

Inventor： Daisaku OGASAHARA

IPC: H04W56/00 ,  H04W72/04

CPC classification number: H04W56/0035 ,  H04B10/548 ,  H04B10/61 ,  H04B10/6164 ,  H04J11/00 ,  H04L27/2657 ,  H04L27/2697 ,  H04W72/0453

Abstract: Because a phase offset occurs between adjoining input blocks of multiple divided blocks when the amount of frequency deviation compensation is dynamically changed, there is the possibility that a restored bit string contains an error. This frequency deviation compensation scheme is equipped with: a frequency deviation compensation means for compensating for a frequency deviation in a frequency-domain signal; and a phase offset compensation means for compensating for a phase offset caused to the signal due to change in an amount of compensation during the frequency compensation.

Abstract translation: 因为当偏移量补偿量动态地改变时，在多个分割块的相邻输入块之间发生相位偏移，所以存在恢复的位串包含错误的可能性。 该频率偏移补偿方案配备有：用于补偿频域信号中的频率偏差的频率偏差补偿装置; 以及相位偏移补偿装置，用于补偿由于频率补偿期间的补偿量的变化而导致的对信号的相位偏移。

公开(公告)号：US20240397351A1

公开(公告)日：2024-11-28

申请号：US18665819

申请日：2024-05-16

Applicant: NEC Corporation

Inventor： Naoto ISHII ,  Toshiki TAKEUCHI ,  Daisaku OGASAHARA

IPC: H04W24/06 ,  H04B10/073 ,  H04Q11/00 ,  H04W88/08

Abstract: A wireless control unit transmits to a plurality of analog sections a control signal for performing control so as to cause the plurality of analog sections to transition to a loopback mode, transmits to the plurality of analog sections an observation signal for observing delay times, calculates, for each of the plurality of analog sections, a path delay based on the number of clocks generated from when the observation signal is transmitted to when the observation signal is received, and transmits to the plurality of analog sections a control signal for canceling the loopback mode of the plurality of analog sections. In addition, the wireless control unit transmits a downlink signal at a timing calculated for each of the plurality of analog sections according to the path delay.

公开(公告)号：US20240396640A1

公开(公告)日：2024-11-28

申请号：US18796721

申请日：2024-08-07

Applicant: NEC Corporation

Inventor： Daisaku OGASAHARA ,  Junichi ABE

IPC: H04B10/61 ,  H04B10/079 ,  H04L27/26

Abstract: When a frequency deviation compensation amount is compensated for by use of frequency shift, a phase offset occurs between adjacent input blocks included in a plurality of input blocks as divided, with the result that an error occurs in a reconstructed bit sequence. A frequency deviation compensation system of the invention is characterized by comprising: a frequency deviation compensation means for compensating for a frequency deviation occurring in a signal by use of frequency shift; and a phase offset compensation means for compensating for a phase offset occurring, in the signal, due to the frequency shift.

公开(公告)号：US20230361882A1

公开(公告)日：2023-11-09

申请号：US18351814

申请日：2023-07-13

Applicant: NEC CORPORATION

Inventor： Daisaku OGASAHARA ,  Junichi ABE

IPC: H04B10/61 ,  H04L27/26 ,  H04B10/079

CPC classification number: H04B10/6164 ,  H04L27/26526 ,  H04B10/0795 ,  H04B10/6165

Abstract: When a frequency deviation compensation amount is compensated for by use of frequency shift, a phase offset occurs between adjacent input blocks included in a plurality of input blocks as divided, with the result that an error occurs in a reconstructed bit sequence. A frequency deviation compensation system of the invention is characterized by comprising: a frequency deviation compensation means for compensating for a frequency deviation occurring in a signal by use of frequency shift; and a phase offset compensation means for compensating for a phase offset occurring, in the signal, due to the frequency shift.

公开(公告)号：US20210044362A1

公开(公告)日：2021-02-11

申请号：US17077501

申请日：2020-10-22

Applicant: NEC Corporation

Inventor： Daisaku OGASAHARA ,  Junichi ABE

IPC: H04B10/61 ,  H04B10/079

Abstract: When a frequency deviation compensation amount is compensated for by use of frequency shift, a phase offset occurs between adjacent input blocks included in a plurality of input blocks as divided, with the result that an error occurs in a reconstructed bit sequence. A frequency deviation compensation system of the invention is characterized by comprising: a frequency deviation compensation means for compensating for a frequency deviation occurring in a signal by use of frequency shift; and a phase offset compensation means for compensating for a phase offset occurring, in the signal, due to the frequency shift.