Abstract:
An amplitude and phase modulation circuit for modulating an M-ary digital signal having pulses onto a carrier wave for transmission by direct digital synthesis. The modulation circuit includes a digital source that generates a digital signal including pulses representing logical 1s and no pulses representing logical zeros, where a group of M pulses represents a constellation point to be transmitted. The modulation circuit further includes a phase control circuit that provides phase control and an amplitude control circuit that provides pulse width control for the constellation point to be transmitted. A saturated amplifier amplifies the phase and amplitude controlled digital signal and a filter integrates and averages the digital signal to remove noise from the signal so as to convert the digital signal to an analog signal, where the digital source operates to reduce the amplifier power consumption requirements.
Abstract:
An apparatus includes: a Global Positioning System (GPS) phased array comprising a plurality of digital beam forming elements (DBFEs), wherein at least one of the DBFEs includes: an antenna configured to transmit a GPS signal; a radio frequency (RF) electronics section operably connected to the antenna and digital electronics sections; and a digital electronics section operably connected to the RF electronics section. An apparatus includes: a GPS phased array comprising a plurality of DBFEs, wherein at least one of the DBFEs includes: an antenna configured to transmit a GPS signal; an RF electronics section operably connected to the antenna and digital electronics sections; and a digital electronics section operably connected an RF electronic section; a navigation encoder and frequency generator (NEFU) unit operably connected to the GPS phased array; and an atomic frequency standard operably connected to the NEFU unit.
Abstract:
An embodiment generates a composite high speed clock with embedded frame synchronization using simple digital encoding of a high speed reference clock. The high speed reference clock and self-aligned frame synchronization signal are recovered by standard logic gate circuitry. The encoding and decoding circuits are comprised of basic digital logic gates with low propagation delay skew and timing jitter. The encoded clock is easier to transmit from source unit to destination unit over common transmission media (i.e., digital transceivers, amplifiers, splitters, connectors and coaxial cable) because only a single interface is required and because the encoding scheme reduces the composite clock to a minimal transmission bandwidth with constrained waveform harmonic content, relative to a low frequency frame sync with fast rise time that requires a broadband transmission media.
Abstract:
An apparatus includes: a Global Positioning System (GPS) phased array comprising a plurality of digital beam forming elements (DBFEs), wherein at least one of the DBFEs includes: an antenna configured to transmit a GPS signal; a radio frequency (RF) electronics section operably connected to the antenna and digital electronics sections; and a digital electronics section operably connected to the RF electronics section. An apparatus includes: a GPS phased array comprising a plurality of DBFEs, wherein at least one of the DBFEs includes: an antenna configured to transmit a GPS signal; an RF electronics section operably connected to the antenna and digital electronics sections; and a digital electronics section operably connected an RF electronic section; a navigation encoder and frequency generator (NEFU) unit operably connected to the GPS phased array; and an atomic frequency standard operably connected to the NEFU unit.