公开(公告)号：US20230297485A1

公开(公告)日：2023-09-21

申请号：US17698668

申请日：2022-03-18

Applicant: NVIDIA CORPORATION

Inventor： Pranav VAIDYA ,  Alan MENEZES ,  Siddharth SHARMA ,  Jin OUYANG ,  Gregory Paul SMITH ,  Timothy J. MCDONALD ,  Shounak KAMALAPURKAR ,  Abhijat RANADE ,  Thomas Melvin OGLETREE

IPC: G06F11/34 ,  G06F21/60 ,  G06F1/10

CPC classification number: G06F11/3409 ,  G06F21/602 ,  G06F1/10

Abstract: Various embodiments include a system for generating performance monitoring data in a computing system. The system includes a unit level counter with a set of counters, where each counter increments during each clock cycle in which a corresponding electronic signal is at a first state, such as a high or low logic level state. Periodically, the unit level counter transmits the counter values to a corresponding counter collection unit. The counter collection unit includes a set of counters that aggregates the values of the counters in multiple unit level counters. Based on certain trigger conditions, the counter collection unit transmits records to a reduction channel. The reduction channel includes a set of counters that aggregates the values of the counters in multiple counter collection units. Each virtual machine executing on the system can access a different corresponding reduction channel, providing secure performance metric data for each virtual machine.

公开(公告)号：US20230025021A1

公开(公告)日：2023-01-26

申请号：US17380375

申请日：2021-07-20

Applicant: NVIDIA CORPORATION

Inventor： Gongyu ZHOU ,  Shounak KAMALAPURKAR ,  Yogesh KULKARNI ,  Thomas Melvin OGLETREE ,  Abhijat RANADE

IPC: G06F11/34 ,  G06F11/30

Abstract: A processing unit can include a performance monitor for monitoring the performance of the processing unit and associated sub-units. The performance monitor can include a state machine. The state machine can be implemented via state machine data entries stored in a memory associated with the performance monitor. A state machine data entry includes information indicating a state transition condition and output signals. The state transition condition includes a current state and input signals required to meet the condition. The output signals include a next state, one or more counter actions, and one or more triggers. The performance monitor implements logic circuits that determine, based on input signals and the state machine data entries, the next state to transition and associated output signals. The state machine data entries can be written and re-written by a user.